sycl-rel_5_2_0: [UR][L0] Enable default support for L0 in-order lists (#13033) #13432
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intel#12983) … info pre-commit PR for oneapi-src/unified-runtime#1429 --------- Signed-off-by: Neil R. Spruit <neil.r.spruit@intel.com> Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
Implement `seq_cst` RC11/ptx6.0 memory consistency for CUDA backend. See https://dl.acm.org/doi/pdf/10.1145/3297858.3304043 and https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#memory-consistency-model for full details. Requires sm_70 or above. With this PR there is now a complete mapping between SYCL memory consistency model capabilities and the official CUDA model, fully exploiting CUDA capabilities when possible on supported arches. This makes the SYCL-CTS atomic_ref tests fully pass for sm_70 on the cuda backend. Fixes intel#11208 Depends on intel#12907 --------- Signed-off-by: JackAKirk <jack.kirk@codeplay.com>
Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
…mmand buffers for L0 (intel#12897)
oneapi-src/unified-runtime#1326 --------- Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
Tests UR PR oneapi-src/unified-runtime#1447 that only reports support for UR command-buffers on ROCm 5.5.1 and later to work around HIP driver bugs related to HIP-Graph in earlier version. This requirement is also explicitly mentioned in the design doc.
…ntel#13014) pre-commit PR for oneapi-src/unified-runtime#1439 --------- Signed-off-by: Neil R. Spruit <neil.r.spruit@intel.com> Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
Signed-off-by: Raiyan Latif <raiyan.latif@intel.com> Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
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Cherry-pick for sycl-rel_5_2_0 depends on #13430
Signed-off-by: Raiyan Latif raiyan.latif@intel.com
Co-authored-by: Kenneth Benzie (Benie) k.benzie@codeplay.com