A simple project, which can facilitate understanding of variables in the "process" statement in VHDL by implementing the following schematics:
Two implementations exist:
- Schematics
- VHDL
A tutorial-like explanation can be found at www.isabekov.pro/four-bit-serial-adder-subtractor
Copyright (C) 2017 Altynbek Isabekov
FourBitSerialAdderSubtractor is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 2 of the License, or (at your option) any later version.
FourBitSerialAdderSubtractor is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License v2.0 for more details.