samples: basic: blinky: eGPIO PoC

PoC of eGPIO peripheral.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>

samples/basic/blinky/CMakeLists.txt

@@ -2,6 +2,13 @@
 
 cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+if(NOT CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP)
+  message(FATAL_ERROR "${BOARD} is not supported for this sample")
+endif()
+
 project(blinky)
 
 target_sources(app PRIVATE src/main.c)
+
+include(ExternalProject)

samples/basic/blinky/Kconfig.sysbuild

@@ -0,0 +1,9 @@
+# Copyright 2023 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config REMOTE_BOARD
+string
+	default "nrf54l15pdk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15pdk"

samples/basic/blinky/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&mbox_cpuapp_rx_cpuflpr 15>, <&mbox_cpuapp_tx_cpuflpr 16>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&mbox_cpuapp_rx_cpuflpr {
+	status = "okay";
+};
+
+&mbox_cpuapp_tx_cpuflpr {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&gpiote20 {
+	status = "disabled";
+};
+
+&gpiote30 {
+	status = "disabled";
+};

samples/basic/blinky/prj.conf

@@ -1 +1,10 @@
-CONFIG_GPIO=y
+#CONFIG_GPIO=y
+
+CONFIG_LOG=n
+CONFIG_PRINTK=y
+
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
+CONFIG_MBOX=y
+
+CONFIG_MULTITHREADING=n

samples/basic/blinky/remote/CMakeLists.txt

@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ipc_service_remote)
+
+target_include_directories(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../common)
+
+target_sources(app PRIVATE src/main.c)

samples/basic/blinky/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,10 @@
+CONFIG_GPIO=y
+
+CONFIG_LOG=n
+CONFIG_PRINTK=y
+
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
+CONFIG_MBOX=y
+
+CONFIG_MULTITHREADING=n

samples/basic/blinky/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&mbox_cpuflpr_rx_cpuapp 16>, <&mbox_cpuflpr_tx_cpuapp 15>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&mbox_cpuflpr_rx_cpuapp {
+	status = "okay";
+};
+
+&mbox_cpuflpr_tx_cpuapp {
+	status = "okay";
+};

samples/basic/blinky/remote/prj.conf

@@ -0,0 +1,10 @@
+CONFIG_GPIO=y
+
+CONFIG_LOG=n
+CONFIG_PRINTK=y
+
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
+CONFIG_MBOX=y
+
+CONFIG_MULTITHREADING=n

samples/basic/blinky/remote/src/main.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <zephyr/ipc/ipc_service.h>
+
+#include <hal/nrf_vpr_csr.h>
+#include <hal/nrf_vpr_csr_vio.h>
+#include <haly/nrfy_gpio.h>
+
+/* 1000 msec = 1 sec */
+#define SLEEP_TIME_MS	(1000)
+#define DATA_SIZE		(100)
+
+struct data_packet {
+	unsigned long cnt;
+	unsigned long size;
+	unsigned char data[DATA_SIZE];
+};
+
+// button2 gpio2 7 -> led0 	gpio0 4
+// button3 gpio2-10 -> gpio2-8
+
+#define PIN_INPUT	(8)
+#define PIN_OUTPUT	(7)
+
+volatile uint32_t bound_sem = 1;
+volatile uint32_t recv_sem = 1;
+volatile uint32_t led_state = 0;
+
+static void ep_bound(void *priv)
+{
+	bound_sem = 0;
+	printk("Ep bounded\n");
+}
+
+static void ep_recv(const void *data, size_t len, void *priv)
+{
+	struct data_packet *packet = (struct data_packet *)data;
+
+	led_state = packet->data[0];
+//	printk("LED state: %s\n", led_state ? "ON" : "OFF");
+
+	recv_sem = 0;
+}
+
+static struct ipc_ept_cfg ep_cfg = {
+	.cb = {
+		.bound    = ep_bound,
+		.received = ep_recv,
+	},
+};
+
+int main(void)
+{
+	int ret;
+	const struct device *ipc0_instance;
+	struct ipc_ept ep;
+
+	ipc0_instance = DEVICE_DT_GET(DT_NODELABEL(ipc0));
+
+	ret = ipc_service_open_instance(ipc0_instance);
+	if ((ret < 0) && (ret != -EALREADY)) {
+		printk("ipc_service_open_instance() failure\n");
+		return ret;
+	}
+
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	if (ret < 0) {
+		printk("ipc_service_register_endpoint() failure\n");
+		return ret;
+	}
+
+	while (bound_sem != 0) {};
+
+	if (!nrf_vpr_csr_rtperiph_enable_check())
+	{
+		printk("rtperiph enable set(true)\n");
+		nrf_vpr_csr_rtperiph_enable_set(true);
+	}
+	else {
+		printk("rtperiph already enabled\n");
+	}
+
+	printk("VIOpins: 0x%08X\n", (uint32_t)nrf_csr_read(VPRCSR_NORDIC_VIOPINS));
+
+// button2 gpio2 7 -> led0 	gpio0 4
+// button3 gpio2-10 -> gpio2-8
+// Mask of pin directions to be set. 0 is input, 1 is output.
+
+	nrfy_gpio_cfg_input(NRF_GPIO_PIN_MAP(2, PIN_INPUT), NRF_GPIO_PIN_PULLUP);
+	nrfy_gpio_pin_control_select(NRF_GPIO_PIN_MAP(2, PIN_INPUT), NRF_GPIO_PIN_SEL_VPR);
+
+	nrfy_gpio_pin_control_select(NRF_GPIO_PIN_MAP(2, PIN_OUTPUT), NRF_GPIO_PIN_SEL_VPR);
+
+	uint16_t gpio_dir = nrf_vpr_csr_vio_dir_get();
+	nrf_vpr_csr_vio_dir_set(gpio_dir | (BIT(PIN_OUTPUT)));
+
+	printf("GPIO dir: 0x%04X\n", nrf_vpr_csr_vio_dir_get());
+
+	while (1) {
+
+		uint16_t gpio_inputs = nrf_vpr_csr_vio_in_get();
+		uint16_t gpio_outs = nrf_vpr_csr_vio_out_get();
+
+		printk("GPIO inputs: 0x%04X, GPIO outputs: 0x%04X\n", gpio_inputs, gpio_outs);
+
+		uint16_t mask_set = (gpio_inputs & (uint16_t)BIT(PIN_INPUT)) ? (uint16_t)0 : (uint16_t)(BIT(PIN_OUTPUT));
+		nrf_vpr_csr_vio_out_set(mask_set);
+
+		printk("GPIO outputs: 0x%04X\n", nrf_vpr_csr_vio_out_get());
+
+		k_busy_wait(SLEEP_TIME_MS*100);
+	}
+	return 0;
+}