Make RSA's interrupt clear field R/W

jessebraham · Oct 22, 2024 · 6f73d6e · 6f73d6e
1 parent 83b6db2
commit 6f73d6e
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Showing 15 changed files with 105 additions and 25 deletions.
diff --git a/esp32c3/src/rsa.rs b/esp32c3/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "RSA query idle register"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
 pub mod int_clr;

diff --git a/esp32c3/src/rsa/int_clr.rs b/esp32c3/src/rsa/int_clr.rs
@@ -1,11 +1,24 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` reader - set this bit to clear RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
 #[doc = "Field `INT_CLR` writer - set this bit to clear RSA interrupt."]
 pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
@@ -16,11 +29,13 @@ impl W {
         INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32c3/svd/patches/esp32c3.yaml b/esp32c3/svd/patches/esp32c3.yaml
@@ -344,3 +344,4 @@ RSA:
     _modify:
       CLEAR_INTERRUPT:
         name: INT_CLR
+        access: read-write
diff --git a/esp32c6/src/rsa.rs b/esp32c6/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "RSA query idle register"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
 pub mod int_clr;

diff --git a/esp32c6/src/rsa/int_clr.rs b/esp32c6/src/rsa/int_clr.rs
@@ -1,11 +1,24 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` reader - set this bit to clear RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
 #[doc = "Field `INT_CLR` writer - set this bit to clear RSA interrupt."]
 pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - set this bit to clear RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
@@ -16,11 +29,13 @@ impl W {
         INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml
@@ -474,3 +474,4 @@ RSA:
     _modify:
       CLEAR_INTERRUPT:
         name: INT_CLR
+        access: read-write
diff --git a/esp32h2/src/rsa.rs b/esp32h2/src/rsa.rs
@@ -179,7 +179,7 @@ pub mod set_start_mult;
 pub type QUERY_IDLE = crate::Reg<query_idle::QUERY_IDLE_SPEC>;
 #[doc = "Represents the RSA status"]
 pub mod query_idle;
-#[doc = "INT_CLR (w) register accessor: Clears RSA interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: Clears RSA interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "Clears RSA interrupt"]
 pub mod int_clr;

diff --git a/esp32h2/src/rsa/int_clr.rs b/esp32h2/src/rsa/int_clr.rs
@@ -1,11 +1,24 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` reader - Write 1 to clear the RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
 #[doc = "Field `INT_CLR` writer - Write 1 to clear the RSA interrupt."]
 pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Write 1 to clear the RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
@@ -16,11 +29,13 @@ impl W {
         INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "Clears RSA interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clears RSA interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml
@@ -490,3 +490,4 @@ RSA:
     _modify:
       CLEAR_INTERRUPT:
         name: INT_CLR
+        access: read-write
diff --git a/esp32s2/src/rsa.rs b/esp32s2/src/rsa.rs
@@ -159,7 +159,7 @@ pub mod mult_start;
 pub type IDLE = crate::Reg<idle::IDLE_SPEC>;
 #[doc = "RSA idle register"]
 pub mod idle;
-#[doc = "INT_CLR (w) register accessor: RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA clear interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA clear interrupt register"]
 pub mod int_clr;

diff --git a/esp32s2/src/rsa/int_clr.rs b/esp32s2/src/rsa/int_clr.rs
@@ -1,11 +1,24 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` reader - Set this bit to 1 to clear the RSA interrupts."]
+pub type INT_CLR_R = crate::BitReader;
 #[doc = "Field `INT_CLR` writer - Set this bit to 1 to clear the RSA interrupts."]
 pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set this bit to 1 to clear the RSA interrupts."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
@@ -16,11 +29,13 @@ impl W {
         INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA clear interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml
@@ -354,6 +354,7 @@ RSA:
     _modify:
       CLEAR_INTERRUPT:
         name: INT_CLR
+        access: read-write
   INT_ENA:
     _modify:
       INTERRUPT_ENA:

diff --git a/esp32s3/src/rsa.rs b/esp32s3/src/rsa.rs
@@ -175,7 +175,7 @@ pub mod mult_start;
 pub type IDLE = crate::Reg<idle::IDLE_SPEC>;
 #[doc = "RSA idle register"]
 pub mod idle;
-#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+#[doc = "INT_CLR (rw) register accessor: RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
 pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
 pub mod int_clr;

diff --git a/esp32s3/src/rsa/int_clr.rs b/esp32s3/src/rsa/int_clr.rs
@@ -1,11 +1,24 @@
+#[doc = "Register `INT_CLR` reader"]
+pub type R = crate::R<INT_CLR_SPEC>;
 #[doc = "Register `INT_CLR` writer"]
 pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` reader - set this bit to 1 to clear the RSA interrupt."]
+pub type INT_CLR_R = crate::BitReader;
 #[doc = "Field `INT_CLR` writer - set this bit to 1 to clear the RSA interrupt."]
 pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - set this bit to 1 to clear the RSA interrupt."]
+    #[inline(always)]
+    pub fn int_clr(&self) -> INT_CLR_R {
+        INT_CLR_R::new((self.bits & 1) != 0)
+    }
+}
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "(not readable)")
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CLR")
+            .field("int_clr", &self.int_clr())
+            .finish()
     }
 }
 impl W {
@@ -16,11 +29,13 @@ impl W {
         INT_CLR_W::new(self, 0)
     }
 }
-#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RSA interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_CLR_SPEC;
 impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
+#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
+impl crate::Readable for INT_CLR_SPEC {}
 #[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;

diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml
@@ -464,6 +464,7 @@ RSA:
     _modify:
       CLEAR_INTERRUPT:
         name: INT_CLR
+        access: read-write
   INT_ENA:
     _modify:
       INTERRUPT_ENA: