Align RSA interrupt clear register/field name for S2/S3 with other chips

jessebraham · Oct 22, 2024 · f7871b8 · f7871b8
1 parent 33e4212
commit f7871b8
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Showing 8 changed files with 90 additions and 78 deletions.
diff --git a/esp32s2/src/rsa.rs b/esp32s2/src/rsa.rs
@@ -13,7 +13,7 @@ pub struct RegisterBlock {
     modmult_start: MODMULT_START,
     mult_start: MULT_START,
     idle: IDLE,
-    clear_interrupt: CLEAR_INTERRUPT,
+    int_clr: INT_CLR,
     constant_time: CONSTANT_TIME,
     search_enable: SEARCH_ENABLE,
     search_pos: SEARCH_POS,
@@ -102,8 +102,8 @@ impl RegisterBlock {
     }
     #[doc = "0x81c - RSA clear interrupt register"]
     #[inline(always)]
-    pub const fn clear_interrupt(&self) -> &CLEAR_INTERRUPT {
-        &self.clear_interrupt
+    pub const fn int_clr(&self) -> &INT_CLR {
+        &self.int_clr
     }
     #[doc = "0x820 - The constant_time option"]
     #[inline(always)]
@@ -159,10 +159,10 @@ pub mod mult_start;
 pub type IDLE = crate::Reg<idle::IDLE_SPEC>;
 #[doc = "RSA idle register"]
 pub mod idle;
-#[doc = "CLEAR_INTERRUPT (w) register accessor: RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clear_interrupt::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear_interrupt`] module"]
-pub type CLEAR_INTERRUPT = crate::Reg<clear_interrupt::CLEAR_INTERRUPT_SPEC>;
+#[doc = "INT_CLR (w) register accessor: RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA clear interrupt register"]
-pub mod clear_interrupt;
+pub mod int_clr;
 #[doc = "CONSTANT_TIME (rw) register accessor: The constant_time option\n\nYou can [`read`](crate::Reg::read) this register and get [`constant_time::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`constant_time::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@constant_time`] module"]
 pub type CONSTANT_TIME = crate::Reg<constant_time::CONSTANT_TIME_SPEC>;
 #[doc = "The constant_time option"]

diff --git a/esp32s2/src/rsa/clear_interrupt.rs b/esp32s2/src/rsa/clear_interrupt.rs
diff --git a/esp32s2/src/rsa/int_clr.rs b/esp32s2/src/rsa/int_clr.rs
@@ -0,0 +1,33 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` writer - Set this bit to 1 to clear the RSA interrupts."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to 1 to clear the RSA interrupts."]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
+    }
+}
+#[doc = "RSA clear interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml
@@ -345,9 +345,15 @@ USB0:
 
 RSA:
   _modify:
+    CLEAR_INTERRUPT:
+      name: INT_CLR
     INTERRUPT_ENA:
       name: INT_ENA
 
+  INT_CLR:
+    _modify:
+      CLEAR_INTERRUPT:
+        name: INT_CLR
   INT_ENA:
     _modify:
       INTERRUPT_ENA:

diff --git a/esp32s3/src/rsa.rs b/esp32s3/src/rsa.rs
@@ -13,7 +13,7 @@ pub struct RegisterBlock {
     modmult_start: MODMULT_START,
     mult_start: MULT_START,
     idle: IDLE,
-    clear_interrupt: CLEAR_INTERRUPT,
+    int_clr: INT_CLR,
     constant_time: CONSTANT_TIME,
     search_enable: SEARCH_ENABLE,
     search_pos: SEARCH_POS,
@@ -102,8 +102,8 @@ impl RegisterBlock {
     }
     #[doc = "0x81c - RSA interrupt clear register"]
     #[inline(always)]
-    pub const fn clear_interrupt(&self) -> &CLEAR_INTERRUPT {
-        &self.clear_interrupt
+    pub const fn int_clr(&self) -> &INT_CLR {
+        &self.int_clr
     }
     #[doc = "0x820 - CONSTANT_TIME option control register"]
     #[inline(always)]
@@ -175,10 +175,10 @@ pub mod mult_start;
 pub type IDLE = crate::Reg<idle::IDLE_SPEC>;
 #[doc = "RSA idle register"]
 pub mod idle;
-#[doc = "CLEAR_INTERRUPT (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clear_interrupt::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear_interrupt`] module"]
-pub type CLEAR_INTERRUPT = crate::Reg<clear_interrupt::CLEAR_INTERRUPT_SPEC>;
+#[doc = "INT_CLR (w) register accessor: RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = "RSA interrupt clear register"]
-pub mod clear_interrupt;
+pub mod int_clr;
 #[doc = "CONSTANT_TIME (rw) register accessor: CONSTANT_TIME option control register\n\nYou can [`read`](crate::Reg::read) this register and get [`constant_time::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`constant_time::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@constant_time`] module"]
 pub type CONSTANT_TIME = crate::Reg<constant_time::CONSTANT_TIME_SPEC>;
 #[doc = "CONSTANT_TIME option control register"]

diff --git a/esp32s3/src/rsa/clear_interrupt.rs b/esp32s3/src/rsa/clear_interrupt.rs
diff --git a/esp32s3/src/rsa/int_clr.rs b/esp32s3/src/rsa/int_clr.rs
@@ -0,0 +1,33 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `INT_CLR` writer - set this bit to 1 to clear the RSA interrupt."]
+pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - set this bit to 1 to clear the RSA interrupt."]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
+        INT_CLR_W::new(self, 0)
+    }
+}
+#[doc = "RSA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml
@@ -455,9 +455,15 @@ LCD_CAM:
 
 RSA:
   _modify:
+    CLEAR_INTERRUPT:
+      name: INT_CLR
     INTERRUPT_ENA:
       name: INT_ENA
 
+  INT_CLR:
+    _modify:
+      CLEAR_INTERRUPT:
+        name: INT_CLR
   INT_ENA:
     _modify:
       INTERRUPT_ENA: