//////////////////////////////////////////////////////////////////////
//                                                                  //                               
//  Author    : G. Andres Mancera                                   //
//  Project   : SystemVerilog Testbench for a 10GE MAC Core         //
//  License   : GNU Lesser General Public License                   //
//                                                                  //
//////////////////////////////////////////////////////////////////////

=================================
  EXECUTIVE SUMMARY
=================================
This is the source code of a fully-fledged SystemVerilog OOP verification
environment.  The Design-Under-Test (DUT) is a 10GE MAC Core whose source 
code is available under the LGPL license from OpenCores.org:
  http://opencores.org/project,xge_mac

This verification environment was developed as the final project of the 
"Advanced Verification With SystemVerilog OOP Testbench" course at the
UCSC Silicon Valley Extension.  For additional information, take a look 
at the verification document available in the doc/ directory.


=================================
  VERIFICATION PLAN DOCUMENT
=================================
The verification plan is available in the doc/ directory.  This document
describes the whole testbench environment and all its components in detail.
An appendix that explains the 2 bugs that were found as part of this project
has been also added to the verification plan.


=================================
  TESTBENCH'S FILE STRUCTURE
=================================
Here is a brief description of each one of the directories in this project:
 * doc/:  PDF verification plan (aka testplan).
 * rtl/:  Verilog source code for the DUT.
 * scripts/:  Scripts required to run a regression.
 * sim/:  Generic runsim files with all the required VCS flags.
 * testbench/:  Source code for all the testbench components.
 * testcases/:  Test case files.


=================================
  HOW TO RUN A TEST/REGRESSION?
=================================
Go to the scripts/ directory and type "make".  This will display the Makefile
usage.  You can choose to run all the test cases at once, or you can also run
individual testcases.  The Makefile also allows you to run a full regression 
and collect coverage information.

If you choose to run a full regression, a perl script will be invoked by the
Makefile in order to parse the log files and generate a report that contains
test cases with a passing/failing/unknown log signature.


=================================
  ADDITIONAL FEATURES
=================================
* SystemVerilog Assertions (SVAs) have been added to the xge_mac_interface 
  to detect incorrect SOP/EOP framing on the packet receive interface.  There
  is also a third assertion to make sure that the pkt_rx_data signal is never 
  driven to 'X' or 'Z' during a valid cycle (i.e., pkt_tx_val is asserted).

* The wishbone interface clock and reset signals have also been appropriately
  wired from the top level.  This allows the testbench to configure the design
  during the initialization phase and to read from the status registers at the 
  end of the test.  The tasks that perform these operations are also part of
  the interface file.  Those tasks are then called from the testcases, as
  shown in testcases/bringup_loopback/testcase.sv