Update README.md

jsummer10 · Apr 26, 2021 · 0f5e272 · 0f5e272
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@@ -19,7 +19,7 @@ Created with the goal of implementing a video compression algorithm
 
 ## Execution 
 
-Core designed and synthesized in Vivado. Implemented on the Xilinx Artix-7 FPGA
+Core designed and synthesized in Vivado and implemented on the Xilinx Artix-7 FPGA
 
 ## Authors