GitHub - kavinxraj/IC2021: System Verilog Circuits

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 62 Commits
filelist		filelist
fpga/amd_xilinx/counters/ripple_counter		fpga/amd_xilinx/counters/ripple_counter
src		src
verif_d/sim_xlm/counters		verif_d/sim_xlm/counters
verif_s		verif_s
.gitignore		.gitignore
README		README
setup.sh		setup.sh

Repository files navigation

verif_d - dynamic verification ( SIM )
verif_s - static verification ( Lint | CDC | FEV | STA )
syn - synthesis
pnr - place and route
bin - project utility binaries ( FLOW | AUTOMATION )
cfg - configuration files for project
src - source directory ( rtl |  upf | tb | uvm_tb | sdc )
docs - documenatation containing circuit diagram and waveform