컴퓨터공학 설계 및 실험 II (CSE3016)
2020년 2학기
| Week | Contents |
|---|---|
| 1주차 | FPGA overview |
| 2주차 | Verilog syntax |
| 3주차 | Loigical Gate |
| 4주차 | Logical Gate applications |
| 5주차 | De Morgan's Laws |
| 6주차 | Adder / Subtractor, Code Converter |
| 7주차 | Parity bit Generator/Checker, 2-bit binary comparator |
| 8주차 | 2 to 4 Decoder, 4 to 2 Encoder, BCD to Decimal Decoder |
| 9주차 | 8 to 1 line MUX, 1 to 4 line deMUX |
| 10주차 | 4 Bit Binary Parallel Adder / Subtractor, BCD Adder |
| 11주차 | RS / D / JK Flip-Flop |
| 12주차 | 2-bit Counter, 4-bit Decade Counter |
| 13주차 | 4-bit Shift Register / Ring Counter / Up-Down counter |
| 14주차 | State / Mealy / Moore Machine, Sequence Detector |