This project aims to develop a tool to graphically view a
place-n-routed ICE40 configuration, showing the exact placement of
every signal and logic gates. It reads the *.asc files that are also
used as input to icepack to generate the final bitstream. HX1K, HX8K, and UP5K
devices are supported.

This is still work in progress, and some connections are not shown,
eg. global nets and BRAM connections. Still, it should already be quite
functional.


The latest version is hosted on github.io for easy access:

  https://knielsen.github.io/ice40_viewer/ice40_viewer.html

See the bottom of the page (below the canvas display) for instructions.


There is also a standalone version available as the program
iceview_html.py. This program reads an input *.asc file and outputs a
standalone .html page containing the viewer. Optionally, the result
can be opened directly in a browser of choice (-s option):

  iceview_html.py -s firefox input.asc output.html

This should provide a convenient way to use the viewer during FPGA
development.


Instructions for installing the HTTP-server version: Dump the files
somewhere accessible through a web server, and open ice40_viewer.html
in a browser.

One really simple way, useful for development, is to use Python's
SimpleHTTPServer. Simply run it from the directory containing the
source files:

  python -m SimpleHTTPServer

Then the tool is available as http://localhost:8000/ice40_viewer.html


License: ISC license, see file LICENSE.

Most of the examples are from https://github.com/nesl/ice40_examples,
and are under a GPL-v3 license, see examples/LICENSE.


Contact: Kristian Nielsen <knielsen@knielsen-hq.org>