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chg: Add suport to set PWM frequency in bitbang_pwm (LEDC for ESP32, …
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…ESP32C3)
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@lcgamboa
lcgamboa committed Jun 22, 2024
1 parent 9d3b757 commit b219091
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Showing 10 changed files with 173 additions and 101 deletions.
48 changes: 24 additions & 24 deletions src/boards/board_Blue_Pill.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -778,14 +778,14 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim2 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 0] = iopin(A, 0);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 0, iopin(A, 0));
}
break;
case 1:
// tim2 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 1] = iopin(A, 1);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 1, iopin(A, 1));
}
break;
case 2:
Expand All @@ -800,7 +800,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim2 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 2] = iopin(A, 2);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 2, iopin(A, 2));
}
break;
case 3:
Expand All @@ -815,7 +815,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim2 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 3] = iopin(A, 3);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 3, iopin(A, 3));
}
break;
case 4:
Expand Down Expand Up @@ -843,7 +843,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim3 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 0] = iopin(A, 6);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 0, iopin(A, 6));
}
break;
case 7:
Expand All @@ -859,20 +859,20 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim1_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 7);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 0, iopin(A, 7));
break;
}
// tim3 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 1] = iopin(A, 7);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 1, iopin(A, 7));
}
break;
case 8:
// tim1 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 8);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 0, iopin(A, 8));
}
break;
case 9:
Expand All @@ -887,7 +887,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim1 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 1] = iopin(A, 9);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 1, iopin(A, 9));
}
break;
case 10:
Expand All @@ -902,14 +902,14 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim1 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 2] = iopin(A, 10);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 2, iopin(A, 10));
}
break;
case 11:
// tim1 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 3] = iopin(A, 11);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 3, iopin(A, 11));
}
break;
case 12:
Expand All @@ -928,26 +928,26 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim1_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 1] = iopin(B, 0);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 1, iopin(B, 0));
break;
}
// tim3_ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 2] = iopin(B, 0);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 2, iopin(B, 0));
}
break;
case 1:
// tim1_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 2] = iopin(B, 1);
bitbang_pwm_set_pin(&pwm_out, (0 << 2) + 2, iopin(B, 1));
break;
}
// tim3_ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 3] = iopin(B, 1);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 3, iopin(B, 1));
}

break;
Expand All @@ -957,14 +957,14 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim2_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 1] = iopin(B, 3);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 1, iopin(B, 3));
break;
}
case 4:
// tim3_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 0] = iopin(B, 4);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 0, iopin(B, 4));
break;
}
case 5:
Expand All @@ -980,7 +980,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim3_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 1] = iopin(B, 5);
bitbang_pwm_set_pin(&pwm_out, (2 << 2) + 1, iopin(B, 5));
break;
}
break;
Expand All @@ -1004,7 +1004,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim4 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 0] = iopin(B, 6);
bitbang_pwm_set_pin(&pwm_out, (3 << 2) + 0, iopin(B, 6));
}
break;
case 7:
Expand All @@ -1027,7 +1027,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim4 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 1] = iopin(B, 7);
bitbang_pwm_set_pin(&pwm_out, (3 << 2) + 1, iopin(B, 7));
}
break;
case 8:
Expand All @@ -1042,7 +1042,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim4 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 2] = iopin(B, 8);
bitbang_pwm_set_pin(&pwm_out, (3 << 2) + 2, iopin(B, 8));
}
case 9:
// i2c0 (alt)
Expand All @@ -1056,14 +1056,14 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim4 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 3] = iopin(B, 9);
bitbang_pwm_set_pin(&pwm_out, (3 << 2) + 3, iopin(B, 9));
}
break;
case 10:
// tim2_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 2] = iopin(B, 10);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 2, iopin(B, 10));
break;
}
/*
Expand All @@ -1090,7 +1090,7 @@ void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
// tim2_ch4n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 3] = iopin(B, 10);
bitbang_pwm_set_pin(&pwm_out, (1 << 2) + 3, iopin(B, 10));
break;
}
/*
Expand Down
16 changes: 12 additions & 4 deletions src/boards/board_C3_DevKitC.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -934,7 +934,7 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
case 49: // ledc_ls_sig_out4
case 50: // ledc_ls_sig_out5
// printf("LEDC channel %i in GPIO %i\n", function - 45, gpio);
pwm_out.pins[function - 45] = io2pin(gpio);
bitbang_pwm_set_pin(&pwm_out, function - 45, io2pin(gpio));
break;
case 51: // rmt_sig_out0
case 52: // rmt_sig_out1
Expand Down Expand Up @@ -1046,9 +1046,17 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
}

} break;
case QEMU_EXTRA_PIN_LEDC_CFG:
bitbang_pwm_set_duty(&pwm_out, (cfg & 0x0F00) >> 8, cfg & 0xFF);
break;
case QEMU_EXTRA_PIN_LEDC_CFG: {
uint32_t* channel_conf0_reg = qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_CHANNEL_CONF); // 16
uint32_t* timer_freq = qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_TIMER_FREQ); // 8
float* channel_duty = (float*)qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_CHANNEL_DUTY); // 16
int channel = (cfg & 0x0F00) >> 8;
int timern = channel_conf0_reg[channel] & 0x03;

bitbang_pwm_set_freq(&pwm_out, channel, timer_freq[timern]);
// bitbang_pwm_set_duty(&pwm_out, channel, cfg & 0xFF);
bitbang_pwm_set_duty_f(&pwm_out, channel, channel_duty[channel]);
} break;
}
}

Expand Down
15 changes: 13 additions & 2 deletions src/boards/board_DevKitC.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -992,7 +992,7 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
case 85: // ledc_ls_sig_out6
case 86: // ledc_ls_sig_out7
// printf("LEDC channel %i in GPIO %i\n",function - 71, gpio);
pwm_out.pins[function - 71] = io2pin(gpio);
bitbang_pwm_set_pin(&pwm_out, function - 71, io2pin(gpio));
break;
case 87: // rmt_sig_out0
// case 88: // rmt_sig_out1 //FIXME only channel 0 enabled
Expand Down Expand Up @@ -1108,7 +1108,18 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {

} break;
case QEMU_EXTRA_PIN_LEDC_CFG:
bitbang_pwm_set_duty(&pwm_out, (cfg & 0x0F00) >> 8, cfg & 0xFF);
uint32_t* channel_conf0_reg = qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_CHANNEL_CONF); // 16
uint32_t* timer_freq = qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_TIMER_FREQ); // 8
float* channel_duty = (float*)qemu_picsimlab_get_internals(QEMU_INTERNAL_LEDC_CHANNEL_DUTY); // 16
int channel = (cfg & 0x0F00) >> 8;
int timern = channel_conf0_reg[channel] & 0x03;
if (channel >= 8) {
timern += 4; // use LSTimers
}

bitbang_pwm_set_freq(&pwm_out, channel, timer_freq[timern]);
// bitbang_pwm_set_duty(&pwm_out, channel, cfg & 0xFF);
bitbang_pwm_set_duty_f(&pwm_out, channel, channel_duty[channel]);
break;
}
}
Expand Down
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