4x4-Multiplier-VHDL-

Authors: Eduardo Brito, Felipe Tormes, Levindo Neto

A 4x4 Multiplier made in VHDL.

Algorithm

The used algorithm can be viewed in the image below:

RTL Project

The RTL Project is divided in:

• ASM Fluxogram
• Control Block (Finite State Machine)
• Operative Block (Registers, Logical Blocks, Functional and Arithmetic Circuits)

ASM Fluxogram

The ASM fluxogram for the RTL project's model can be seen in the following image:

Control Block

The finite state machine for the 4x4 Multiplier can be viewed in the image below:

Operative Block

The operative part, with the used registers, logical and arithmetic digital blocks, can be viewed in the image below:

Memory Organization

The memory of the 4x4 multiplier is organized in:

• Two single-port memories with 4 positions of 16 bits each for the input matrices.
• One single-port memory with 16 positions of 8 bits each for the output matrix. The organization of the used memory can be viewed in the following image:

High Level Circuit

The built circuit, in a high level approach, can be seen in the image below:

Temporal Simulations

Simulation Without Delay

Simulation with Delay

Other Information

Area Information

Temporal Information

Number of Cycles: 154.
Time to Answer: 1535ns using 10 ns of period.
Minimum Period: 10.233ns.
Maximum Frequency: 97.723MHz.
Minimum Input Arrival Time before Clock: 2.382ns.
Maximum Output, which is the Required Time after Clock: 6.446ns.