Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix software path #72

Merged
merged 2 commits into from
Nov 2, 2023
Merged

Fix software path #72

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
ba520fe
Fix path to blank memory file
marnovandermaas Oct 31, 2023
af7a82e
Fix software path in Nix flake
marnovandermaas Oct 31, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions flake.nix
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,22 +110,22 @@
helpstr=$(cat <<'EOF'

Build ibex software :
mkdir sw/build && pushd sw/build && cmake ../ && make && popd
mkdir sw/c/build && pushd sw/c/build && cmake ../ && make && popd
Build ibex simulation verilator model :
fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
Run ibex simulator verilator model :
./build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system -t \
--meminit=ram,sw/build/demo/hello_world/demo
--meminit=ram,sw/c/build/demo/hello_world/demo
Build ibex-demo-system FPGA bitstream for Arty-A7 :
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system
Program Arty-A7 FPGA with bitstream :
openFPGALoader -b arty_a7_35t build/lowrisc_ibex_demo_system_0/synth-vivado/lowrisc_ibex_demo_system_0.bit
Load ibex software to the programmed FPGA :
./util/load_demo_system.sh run ./sw/build/demo/lcd_st7735/lcd_st7735
./util/load_demo_system.sh run ./sw/c/build/demo/lcd_st7735/lcd_st7735
Start an OpenOCD instance, connected to the Arty-A7 ibex
openocd -f util/arty-a7-openocd-cfg.tcl
Connect gdb to a running program on the FPGA (In a different terminal to the OpenOCD instance):
riscv32-unknown-elf-gdb -ex "target extended-remote localhost:3333" ./sw/build/demo/hello_world/demo
riscv32-unknown-elf-gdb -ex "target extended-remote localhost:3333" ./sw/c/build/demo/hello_world/demo

To leave the environment:
exit
Expand Down
2 changes: 1 addition & 1 deletion ibex_demo_system.core
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ parameters:
SRAMInitFile:
datatype: str
description: SRAM initialization file in vmem hex format
default: "../../../../../sw/build/blank/blank.vmem"
default: "../../../../../sw/c/build/blank/blank.vmem"
paramtype: vlogparam

# For value definition, please see ip/prim/rtl/prim_pkg.sv
Expand Down