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Updated verilator waivers so the sim builds #91

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Updated verilator waivers so the sim builds #91

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4 changes: 3 additions & 1 deletion dv/verilator/demo_system_verilator_lint.vlt
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Original file line number Diff line number Diff line change
Expand Up @@ -25,4 +25,6 @@ lint_off -rule PINMISSING -file "*pulp_riscv_dbg*"
lint_off -rule UNUSED -file "*ibex_register_file_fpga*"

lint_off -rule UNOPTFLAT -file "*/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv"
lint_off -rule WIDTHEXPAND -file "*pulp_riscv_dbg/src/dm_mem.sv"
lint_off -rule WIDTH -file "*pulp_riscv_dbg/src/dm_mem.sv"
lint_off -rule UNDRIVEN -file "*ibex_register_file_fpga.sv"
lint_off -rule IMPERFECTSCH -file "*prim_flop_2sync.sv"
5 changes: 0 additions & 5 deletions ibex_demo_system_core.core
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Expand Up @@ -22,12 +22,7 @@ filesets:
- rtl/system/spi_top.sv
file_type: systemVerilogSource

files_lint_verilator:
files:
- lint/verilator_waiver.vlt: {file_type: vlt}

targets:
default:
filesets:
- tool_verilator ? (files_lint_verilator)
- files_rtl_demo_system
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