Skip to content
pr-lint

[rtl] Fix counter reset value on FPGA #239

Sign in to view logs

[rtl] Fix counter reset value on FPGA

[rtl] Fix counter reset value on FPGA #239

Triggered via pull request November 27, 2024 14:31
@nasahlpanasahlpa
opened #2226
nasahlpa:fix_counter_reset_value
Status Success
Total duration 55s
Artifacts 1

pr_lint.yml

on: pull_request
verible-lint
44s
verible-lint
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size
verible-linter
2.5 KB