[rtl] Fix FI vulnerability in RF #12
nasahlpaAnnotations
1 error and 3 warnings
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verible-lint
Process completed with exit code 1.
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verible-lint:
rtl/ibex_register_file_fpga.sv#L133
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./rtl/ibex_register_file_fpga.sv" range:{start:{line:133 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_register_file_ff.sv#L213
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./rtl/ibex_register_file_ff.sv" range:{start:{line:213 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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verible-lint:
rtl/ibex_register_file_latch.sv#L150
[verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./rtl/ibex_register_file_latch.sv" range:{start:{line:150 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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