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Update google_riscv-dv to chipsalliance/riscv-dv@71666eb
Update code from upstream repository https://github.com/chipsalliance/riscv-dv to revision 71666ebacd69266b1abb7cdbad5e1897ce5884e6 * Fixes to support RV32 (Maciej Kurc) * Extend CI matrix (Eryk Szpotanski) * Add pyflow test (Grzegorz Placzek) * Allow the CI to run from any branch and any PR (Maciej Kurc) * [pmp] Remove MSECCFG reads from trap handler when Smepmp is disabled (Marno van der Maas) Signed-off-by: Greg Chadwick <gac@lowrisc.org>
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#!/usr/bin/env python3 | ||
import argparse | ||
import re | ||
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# ============================================================================= | ||
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class AssemblyLine: | ||
""" | ||
Simple assembly line representation | ||
""" | ||
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RE_INSTR = re.compile(r"(?P<mnemonic>\S+)\s+(?P<operands>.*)") | ||
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def __init__(self, text): | ||
self.text = text | ||
self.mnemonic = None | ||
self.operands = None | ||
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# Strip label if any | ||
if ":" in text: | ||
text = text.split(":", maxsplit=1)[1] | ||
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# Strip comment if any | ||
if "#" in text: | ||
text = text.split("#", maxsplit=1)[0] | ||
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# Get instruction and operands | ||
m = self.RE_INSTR.match(text.strip()) | ||
if m is not None: | ||
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if m.group("mnemonic")[0] == ".": | ||
return | ||
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self.mnemonic = m.group("mnemonic").lower() | ||
self.operands = [op.strip() for op in m.group("operands").split()] | ||
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def __str__(self): | ||
return self.text | ||
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# ============================================================================= | ||
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def main(): | ||
parser = argparse.ArgumentParser() | ||
parser.add_argument( | ||
"-i", | ||
type=str, | ||
required=True, | ||
help="Input assembly file" | ||
) | ||
parser.add_argument( | ||
"-o", | ||
type=str, | ||
required=True, | ||
help="Output assembly file" | ||
) | ||
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args = parser.parse_args() | ||
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max_nops = 10 | ||
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# Read and parse | ||
with open(args.i, "r") as fp: | ||
inp_lines = [AssemblyLine(l) for l in fp.readlines()] | ||
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# Identify a delayed write instruction followed by another one which writes | ||
# to the same register | ||
out_lines = [] | ||
for i in range(len(inp_lines)): | ||
line = inp_lines[i] | ||
out_lines.append(line) | ||
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# Bypass | ||
if not line.mnemonic: | ||
continue | ||
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# Check if it is a delayed write. If not then bypass | ||
is_delayed = line.mnemonic in ["div", "divu", "rem", "remu", "lw"] | ||
if not is_delayed: | ||
continue | ||
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# Get next 2 instructions | ||
following = [] | ||
for j in range(i+1, len(inp_lines)): | ||
if inp_lines[j].mnemonic is not None: | ||
following.append(inp_lines[j]) | ||
if len(following) >= 2: | ||
break | ||
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# If any of the instructions targets the same register insert NOPs | ||
dst = line.operands[0] | ||
for j, l in enumerate(following): | ||
if l.operands and l.operands[0] == dst: | ||
nops = max(0, max_nops - j) | ||
for _ in range(nops): | ||
out_lines.append(" " * 18 + "nop # FIXME: A fixup not to make VeeR cancel a delayed write\n") | ||
break | ||
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# Write | ||
with open(args.o, "w") as fp: | ||
for l in out_lines: | ||
fp.write(str(l)) | ||
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if __name__ == "__main__": | ||
main() |
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import sys | ||
from json import dumps | ||
from yaml import load, Loader | ||
from typing import Generator | ||
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def parse_yaml(path: str) -> Generator[str, None, None]: | ||
with open(path, 'rb') as fd: | ||
tests = load(fd, Loader=Loader) | ||
for test in tests: | ||
if 'import' in test: | ||
import_path = test['import'].split('/', 1)[1] | ||
yield from parse_yaml(import_path) | ||
elif 'test' in test: | ||
yield test['test'] | ||
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if __name__ == "__main__": | ||
if len(sys.argv) == 2: | ||
testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml') | ||
else: | ||
testlist = parse_yaml('yaml/base_testlist.yaml') | ||
testlist = list(testlist) | ||
# remove, will cause incomplete sim, need customized RTL | ||
testlist.remove("riscv_csr_test") | ||
print(dumps(testlist)) |
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# https://github.com/chipsalliance/Cores-VeeR-EL2/blob/774510e43f5408ec2b818db8f865027bc9be97b8/.github/workflows/build-spike.yml | ||
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name: Spike Build | ||
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on: | ||
workflow_call: | ||
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jobs: | ||
verilator: | ||
name: Build Spike | ||
runs-on: ubuntu-latest | ||
env: | ||
TOOL_NAME: spike | ||
TOOL_VERSION: d70ea67d | ||
DEBIAN_FRONTEND: "noninteractive" | ||
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steps: | ||
- name: Setup Cache Metadata | ||
id: cache_metadata | ||
run: | | ||
cache_date=$(date +"%Y_%m_%d") | ||
cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }} | ||
echo "Cache date: "$cache_date | ||
echo "Cache name: "$cache_name | ||
echo "cache_date=$cache_date" >> "$GITHUB_ENV" | ||
echo "cache_name=$cache_name" >> "$GITHUB_ENV" | ||
- name: Setup cache | ||
uses: actions/cache@v3 | ||
id: cache | ||
timeout-minutes: 60 | ||
with: | ||
path: | | ||
/opt/spike | ||
/opt/spike/.cache | ||
key: ${{ env.cache_name }}_${{ env.cache_date }} | ||
restore-keys: ${{ env.cache_name }}_ | ||
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- name: Install prerequisities | ||
if: ${{ steps.cache.outputs.cache-hit != 'true' }} | ||
run: | | ||
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ | ||
git build-essential cmake ccache device-tree-compiler | ||
- name: Build Spike | ||
if: ${{ steps.cache.outputs.cache-hit != 'true' }} | ||
run: | | ||
export CCACHE_DIR=/opt/spike/.cache | ||
ccache --show-config | grep cache_dir | ||
git clone https://github.com/riscv-software-src/riscv-isa-sim spike | ||
export CC="ccache gcc" | ||
export CXX="ccache g++" | ||
pushd spike | ||
git checkout ${{ env.TOOL_VERSION }} | ||
mkdir build | ||
cd build | ||
../configure --prefix=/opt/spike | ||
make -j`nproc` | ||
make install | ||
popd | ||
rm -rf /opt/spike/include # Remove include and lib to save space | ||
rm -rf /opt/spike/lib | ||
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vendor/google_riscv-dv/.github/workflows/metrics-regress.yml
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