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[formal/conn] Fix clkmgr peri clock
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Remove units that are not connected to peripheral clocks.
Add missing peripheral clock connections.

Signed-off-by: Guillermo Maturana <maturana@google.com>
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@matutem
matutem committed Sep 27, 2021
1 parent 2fb857a commit 2280cad
Showing 1 changed file with 4 additions and 2 deletions.
6 changes: 4 additions & 2 deletions hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,10 +22,12 @@ CONNECTION,CLKMGR_PERI_CLK0_I2C0,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_
CONNECTION,CLKMGR_PERI_CLK0_I2C1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_i2c1,clk_i
CONNECTION,CLKMGR_PERI_CLK0_I2C2,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_i2c2,clk_i
CONNECTION,CLKMGR_PERI_CLK0_PATTGEN,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_pattgen,clk_i
CONNECTION,CLKMGR_PERI_CLK0_UART0,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart0,clk_i
CONNECTION,CLKMGR_PERI_CLK0_UART1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart1,clk_i
CONNECTION,CLKMGR_PERI_CLK0_UART2,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart2,clk_i
CONNECTION,CLKMGR_PERI_CLK0_UART3,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart3,clk_i
CONNECTION,CLKMGR_PERI_CLK0_USBDEV,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_usbdev,clk_i
CONNECTION,CLKMGR_PERI_CLK0_ADC_CTRL_AON,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_adc_ctrl_aon,clk_i
CONNECTION,CLKMGR_PERI_CLK0_SRAM_CTRL_RET_AON,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_sram_ctrl_ret_aon,clk_i
CONNECTION,CLKMGR_PERI_CLK0_SRAM_CTRL_RET_AON_OTP,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_sram_ctrl_ret_aon,clk_otp_i
CONNECTION,CLKMGR_PERI_CLK1_SPI_DEVICE,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div2_peri,top_earlgrey.u_spi_device,scan_clk_i
CONNECTION,CLKMGR_PERI_CLK1_SPI_HOST0,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_peri,top_earlgrey.u_spi_host0,clk_core_i
CONNECTION,CLKMGR_PERI_CLK1_SPI_HOST1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div2_peri,top_earlgrey.u_spi_host1,clk_core_i
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