[hw,prim,ram_2p] Add DFT response channel

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
lowRISC · Dec 24, 2024 · 5b8c392 · 5b8c392
1 parent 5a9aa5d
commit 5b8c392
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Showing 21 changed files with 310 additions and 62 deletions.
diff --git a/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv b/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
@@ -127,7 +127,8 @@ if (FpgaSram == 1) begin : g_sram_fpga
     .b_wmask_i (r_sram_wmask ),
     .b_rdata_o (r_sram_rdata ),
 
-    .cfg_i ('0)
+    .cfg_i     ('0),
+    .cfg_rsp_o ()
   );
 end else begin : g_sram_ff
   logic [SramDw-1:0] mem [2**SramAw];

diff --git a/hw/ip/prim/prim_ram_1r1w.core b/hw/ip/prim/prim_ram_1r1w.core
@@ -9,6 +9,7 @@ filesets:
   primgen_dep:
     depend:
       - lowrisc:prim:prim_pkg
+      - lowrisc:prim:ram_1p_pkg
       - lowrisc:prim:ram_2p_pkg
       - lowrisc:prim:primgen
 

diff --git a/hw/ip/prim/rtl/prim_ram_1r1w_adv.sv b/hw/ip/prim/rtl/prim_ram_1r1w_adv.sv
@@ -50,7 +50,8 @@ module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
   output logic             b_rvalid_o, // read response (b_rdata_o) is valid
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_t      cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_rsp_o
 );
 
   prim_ram_1r1w_async_adv #(
@@ -77,7 +78,8 @@ module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
     .b_rdata_o,
     .b_rvalid_o,
     .b_rerror_o,
-    .cfg_i
+    .cfg_i,
+    .cfg_rsp_o
   );
 
 endmodule : prim_ram_1r1w_adv
diff --git a/hw/ip/prim/rtl/prim_ram_1r1w_async_adv.sv b/hw/ip/prim/rtl/prim_ram_1r1w_async_adv.sv
@@ -53,7 +53,8 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_t      cfg_i,
+  output ram_2p_cfg_t      cfg_rsp_o
 );
 
 
@@ -91,6 +92,7 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
   logic [Width-1:0]        b_rdata_q,  b_rdata_d ;
   logic [TotalWidth-1:0]   b_rdata_sram ;
   logic [1:0]              b_rerror_q, b_rerror_d ;
+  prim_ram_1p_pkg::ram_1p_cfg_rsp_t cfg_rsp;
 
   prim_ram_1r1w #(
     .MemInitFile     (MemInitFile),
@@ -111,9 +113,13 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
     .b_addr_i   (b_addr_q),
     .b_rdata_o  (b_rdata_sram),
 
-    .cfg_i
+    .cfg_i,
+    .cfg_rsp_o  (cfg_rsp)
   );
 
+  // DFT responeses need to match between prim_ram_1p and prim_ram_2p
+  assign cfg_rsp_o = ram_2p_cfg_rsp_t'(cfg_rsp);
+
   always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
     if (!rst_b_ni) begin
       b_rvalid_sram_q <= 1'b0;

diff --git a/hw/ip/prim/rtl/prim_ram_2p_async_adv.sv b/hw/ip/prim/rtl/prim_ram_2p_async_adv.sv
@@ -58,7 +58,8 @@ module prim_ram_2p_async_adv import prim_ram_2p_pkg::*; #(
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_t      cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_rsp_o
 );
 
 
@@ -129,7 +130,8 @@ module prim_ram_2p_async_adv import prim_ram_2p_pkg::*; #(
     .b_wmask_i  (b_wmask_q),
     .b_rdata_o  (b_rdata_sram),
 
-    .cfg_i
+    .cfg_i,
+    .cfg_rsp_o
   );
 
   always_ff @(posedge clk_a_i or negedge rst_a_ni) begin

diff --git a/hw/ip/prim/prim_ram_2p_pkg.core → ...prim_generic/prim_generic_ram_2p_pkg.core b/hw/ip/prim/prim_ram_2p_pkg.core → ...prim_generic/prim_generic_ram_2p_pkg.core
@@ -3,8 +3,11 @@ CAPI=2:
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-name: "lowrisc:prim:ram_2p_pkg"
+name: "lowrisc:prim_generic:ram_2p_pkg"
 description: "Ram 2p package"
+virtual:
+  - "lowrisc:prim:ram_2p_pkg"
+
 filesets:
   files_rtl:
     files:

diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv
@@ -28,7 +28,8 @@ module prim_generic_ram_1r1w import prim_ram_2p_pkg::*; #(
   input        [Aw-1:0]    b_addr_i,
   output logic [Width-1:0] b_rdata_o,
 
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_t      cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_rsp_o
 );
 
 // For certain synthesis experiments we compile the design with generic models to get an unmapped
@@ -43,6 +44,7 @@ module prim_generic_ram_1r1w import prim_ram_2p_pkg::*; #(
 
   logic unused_cfg;
   assign unused_cfg = ^cfg_i;
+  assign cfg_rsp_o.done = 1'b0;
 
   // Width of internal write mask. Note *_wmask_i input into the module is always assumed
   // to be the full bit mask.

diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv
@@ -32,7 +32,8 @@ module prim_generic_ram_2p import prim_ram_2p_pkg::*; #(
   input  logic [Width-1:0] b_wmask_i,
   output logic [Width-1:0] b_rdata_o,
 
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_t      cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_rsp_o
 );
 
 // For certain synthesis experiments we compile the design with generic models to get an unmapped
@@ -47,6 +48,7 @@ module prim_generic_ram_2p import prim_ram_2p_pkg::*; #(
 
   logic unused_cfg;
   assign unused_cfg = ^cfg_i;
+  assign cfg_rsp_o.done = 1'b0;
 
   // Width of internal write mask. Note *_wmask_i input into the module is always assumed
   // to be the full bit mask.

diff --git a/hw/ip/prim/rtl/prim_ram_2p_pkg.sv → hw/ip/prim_generic/rtl/prim_ram_2p_pkg.sv b/hw/ip/prim/rtl/prim_ram_2p_pkg.sv → hw/ip/prim_generic/rtl/prim_ram_2p_pkg.sv
@@ -20,4 +20,8 @@ package prim_ram_2p_pkg;
 
   parameter ram_2p_cfg_t RAM_2P_CFG_DEFAULT = '0;
 
+  typedef struct packed {
+    logic done;
+  } ram_2p_cfg_rsp_t;
+
 endpackage // prim_ram_2p_pkg
diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
@@ -280,9 +280,27 @@
     { struct:  "ram_2p_cfg",
       package: "prim_ram_2p_pkg",
       type:    "uni",
-      name:    "ram_cfg",
+      name:    "ram_cfg_sys2spi",
       act:     "rcv"
     }
+    { struct:  "ram_2p_cfg",
+      package: "prim_ram_2p_pkg",
+      type:    "uni",
+      name:    "ram_cfg_rsp_sys2spi",
+      act:     "req"
+    }
+    { struct:  "ram_2p_cfg",
+      package: "prim_ram_2p_pkg",
+      type:    "uni",
+      name:    "ram_cfg_spi2sys",
+      act:     "rcv"
+    }
+    { struct:  "ram_2p_cfg",
+      package: "prim_ram_2p_pkg",
+      type:    "uni",
+      name:    "ram_cfg_rsp_spi2sys",
+      act:     "req"
+    }
     { struct:  "passthrough",
       package: "spi_device_pkg"
       type:    "req_rsp"

diff --git a/hw/ip/spi_device/doc/interfaces.md b/hw/ip/spi_device/doc/interfaces.md
@@ -18,13 +18,16 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 
 ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)
 
-| Port Name   | Package::Struct             | Type    | Act   |   Width | Description   |
-|:------------|:----------------------------|:--------|:------|--------:|:--------------|
-| ram_cfg     | prim_ram_2p_pkg::ram_2p_cfg | uni     | rcv   |       1 |               |
-| passthrough | spi_device_pkg::passthrough | req_rsp | req   |       1 |               |
-| mbist_en    | logic                       | uni     | rcv   |       1 |               |
-| sck_monitor | logic                       | uni     | req   |       1 |               |
-| tl          | tlul_pkg::tl                | req_rsp | rsp   |       1 |               |
+| Port Name           | Package::Struct             | Type    | Act   |   Width | Description   |
+|:--------------------|:----------------------------|:--------|:------|--------:|:--------------|
+| ram_cfg_sys2spi     | prim_ram_2p_pkg::ram_2p_cfg | uni     | rcv   |       1 |               |
+| ram_cfg_rsp_sys2spi | prim_ram_2p_pkg::ram_2p_cfg | uni     | req   |       1 |               |
+| ram_cfg_spi2sys     | prim_ram_2p_pkg::ram_2p_cfg | uni     | rcv   |       1 |               |
+| ram_cfg_rsp_spi2sys | prim_ram_2p_pkg::ram_2p_cfg | uni     | req   |       1 |               |
+| passthrough         | spi_device_pkg::passthrough | req_rsp | req   |       1 |               |
+| mbist_en            | logic                       | uni     | rcv   |       1 |               |
+| sck_monitor         | logic                       | uni     | req   |       1 |               |
+| tl                  | tlul_pkg::tl                | req_rsp | rsp   |       1 |               |
 
 ## Interrupts
 

diff --git a/hw/ip/spi_device/pre_dv/tb/spid_readcmd_tb.sv b/hw/ip/spi_device/pre_dv/tb/spid_readcmd_tb.sv
@@ -846,7 +846,8 @@ module tb;
     .b_rdata_o  (spi_mem_rdata),
     .b_rerror_o (spi_mem_rerror),
 
-    .cfg_i      ('0)
+    .cfg_i      ('0),
+    .cfg_rsp_o  ()
   );
 
 

diff --git a/hw/ip/spi_device/pre_dv/tb/spid_upload_tb.sv b/hw/ip/spi_device/pre_dv/tb/spid_upload_tb.sv
@@ -583,7 +583,8 @@ module spid_upload_tb;
     .b_rdata_o  (spi_mem_rdata),
     .b_rerror_o (spi_mem_rerror),
 
-    .cfg_i      ('0)
+    .cfg_i      ('0),
+    .cfg_rsp_o  ()
   );
 
   // Arbiter for bus clock

diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
@@ -53,7 +53,12 @@ module spi_device
   output logic intr_tpm_rdfifo_drop_o,
 
   // Memory configuration
-  input prim_ram_2p_pkg::ram_2p_cfg_t ram_cfg_i,
+  // When using a dual port RAM primitive only this RAM config port is used
+  input  prim_ram_2p_pkg::ram_2p_cfg_t     ram_cfg_sys2spi_i,
+  output prim_ram_2p_pkg::ram_2p_cfg_rsp_t ram_cfg_rsp_sys2spi_o,
+  // When using a 1R1W RAM primitive, both RAM config ports are used
+  input  prim_ram_2p_pkg::ram_2p_cfg_t     ram_cfg_spi2sys_i,
+  output prim_ram_2p_pkg::ram_2p_cfg_rsp_t ram_cfg_rsp_spi2sys_o,
 
   // External clock sensor
   output logic sck_monitor_o,
@@ -1815,31 +1820,34 @@ module spi_device
     .EnableInputPipeline (0),
     .EnableOutputPipeline(0)
   ) u_spid_dpram (
-    .clk_sys_i      (clk_i),
-    .rst_sys_ni     (rst_ni),
-
-    .clk_spi_i      (clk_spi_in_buf),
-    .rst_spi_ni     (spi_dpram_rst_n),
-
-    .sys_req_i      (mem_a_req),
-    .sys_write_i    (mem_a_write),
-    .sys_addr_i     (mem_a_addr),
-    .sys_wdata_i    (mem_a_wdata),
-    .sys_wmask_i    (mem_a_wmask),
-    .sys_rvalid_o   (mem_a_rvalid),
-    .sys_rdata_o    (mem_a_rdata),
-    .sys_rerror_o   (mem_a_rerror),
-
-    .spi_req_i      (mem_b_req),
-    .spi_write_i    (mem_b_write),
-    .spi_addr_i     (mem_b_addr),
-    .spi_wdata_i    (mem_b_wdata),
-    .spi_wmask_i    (mem_b_wmask),
-    .spi_rvalid_o   (mem_b_rvalid),
-    .spi_rdata_o    (mem_b_rdata),
-    .spi_rerror_o   (mem_b_rerror),
-
-    .cfg_i          (ram_cfg_i)
+    .clk_sys_i         (clk_i),
+    .rst_sys_ni        (rst_ni),
+
+    .clk_spi_i         (clk_spi_in_buf),
+    .rst_spi_ni        (spi_dpram_rst_n),
+
+    .sys_req_i         (mem_a_req),
+    .sys_write_i       (mem_a_write),
+    .sys_addr_i        (mem_a_addr),
+    .sys_wdata_i       (mem_a_wdata),
+    .sys_wmask_i       (mem_a_wmask),
+    .sys_rvalid_o      (mem_a_rvalid),
+    .sys_rdata_o       (mem_a_rdata),
+    .sys_rerror_o      (mem_a_rerror),
+
+    .spi_req_i         (mem_b_req),
+    .spi_write_i       (mem_b_write),
+    .spi_addr_i        (mem_b_addr),
+    .spi_wdata_i       (mem_b_wdata),
+    .spi_wmask_i       (mem_b_wmask),
+    .spi_rvalid_o      (mem_b_rvalid),
+    .spi_rdata_o       (mem_b_rdata),
+    .spi_rerror_o      (mem_b_rerror),
+
+    .cfg_sys2spi_i     (ram_cfg_sys2spi_i),
+    .cfg_rsp_sys2spi_o (ram_cfg_rsp_sys2spi_o),
+    .cfg_spi2sys_i     (ram_cfg_spi2sys_i),
+    .cfg_rsp_spi2sys_o (ram_cfg_rsp_spi2sys_o)
   );
 
   // Register module

diff --git a/hw/ip/spi_device/rtl/spid_dpram.sv b/hw/ip/spi_device/rtl/spid_dpram.sv
@@ -45,8 +45,13 @@ module spid_dpram
   output logic [SramDw-1:0]  spi_rdata_o,
   output logic [1:0]         spi_rerror_o,
 
-  input ram_2p_cfg_t         cfg_i
-  );
+  // When using a dual port RAM primitive only this RAM config port is used
+  input  ram_2p_cfg_t        cfg_sys2spi_i,
+  output ram_2p_cfg_rsp_t    cfg_rsp_sys2spi_o,
+  // When using a 1R1W RAM primitive, both RAM config ports are used
+  input  ram_2p_cfg_t        cfg_spi2sys_i,
+  output ram_2p_cfg_rsp_t    cfg_rsp_spi2sys_o
+);
 
   // SYS Wr, SPI Rd is for eFlash, Mailbox, and SFDP
   localparam sram_addr_t     Sys2SpiOffset   = SramEgressIdx;
@@ -158,7 +163,8 @@ module spid_dpram
       .b_rdata_o  (spi_rdata_o),
       .b_rerror_o (spi_rerror_o),
 
-      .cfg_i
+      .cfg_i      (cfg_sys2spi_i),
+      .cfg_rsp_o  (cfg_rsp_sys2spi_o)
     );
 
     logic sys2spi_unused;
@@ -174,8 +180,10 @@ module spid_dpram
       spi2sys_wr_req,
       spi2sys_wr_addr,
       spi2sys_rd_req,
-      spi2sys_rd_addr
+      spi2sys_rd_addr,
+      cfg_spi2sys_i
     };
+    assign cfg_rsp_spi2sys_o = '0;
   end else if (SramType == SramType1r1w) begin : gen_ram1r1w
     prim_ram_1r1w_async_adv #(
       .Depth                     (Sys2SpiDepth),
@@ -202,7 +210,8 @@ module spid_dpram
       .b_rvalid_o                (spi_rvalid_o),
       .b_rerror_o                (spi_rerror_o),
 
-      .cfg_i
+      .cfg_i                     (cfg_sys2spi_i),
+      .cfg_rsp_o                 (cfg_rsp_sys2spi_o)
     );
 
     prim_ram_1r1w_async_adv #(
@@ -231,7 +240,8 @@ module spid_dpram
       .b_rvalid_o                (sys_rvalid_o),
       .b_rerror_o                (sys_rerror_o),
 
-      .cfg_i
+      .cfg_i                     (cfg_spi2sys_i),
+      .cfg_rsp_o                 (cfg_rsp_spi2sys_o)
     );
   end