Single cycle mult #295
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Single cycle mult #295
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Need a minimum of 2 (this is what is used in OpenTitan) to enable back to back requests without stall cycles.
Update code from upstream repository https://github.com/lowrisc/cheriot-ibex.git to revision ea2df9db3bcea776f0dc72d6d89c31c73798ecd4 * Feed RV32M through ibexc_top_tracing/ibexc_top (Greg Chadwick) * Switch to no bitmanip by default (Greg Chadwick) * Feed RV32B through in ibexc_top (Greg Chadwick) Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This is effectively a no-op change. Before the latest Ibex was vendored we had no bitmanip (the RV32BFull parameter was not fully passed through) and RV32M was the fast multiplier. Sadly the single cycle multiplier seems to be increasing timing pressure. It does just meet timing but greatly increases synthesis times. As it's implemented with in-built FPGA DSP blocks it shouldn't be a big issue to use it so something to examine here but for now leave things as they are.
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For reviewing this is the relevant commit 03d918a |
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Converting to draft until SRAM PR is done. |
| @@ -734,7 +734,7 @@ module sonata_system | |||
| .HeapBase ( tl_main_pkg::ADDR_SPACE_SRAM ), | |||
| .TSMapBase ( tl_main_pkg::ADDR_SPACE_REV_TAG ), | |||
| .TSMapSize ( RevTagDepth ), | |||
| .RV32M ( ibex_pkg::RV32MFast ), | |||
| .RV32M ( ibex_pkg::RV32MSingleCycle ), | |||
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In principle looks fine to me as long as we can meet timing.
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Closing in favour of #314 |
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This sits on top of #279 and shouldn't be merged until that has been merged.
Using v2021.1 enabling the single cycle multiplier works fine, no major change in implementation time and implementation results are good. I'd avoided doing it initially as it wasn't working so well under v2023.1/v2024.1 but as has been discovered those versions don't implement Sonata as well for whatever reason (#289)