Hardware revoker control re-mastered #358
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Update code from upstream repository https://github.com/microsoft/cheriot-safe.git to revision 5fd7f427a65da675bd214e752c3e30fc1d19a54a * Factor tbre_go logic into write operations (Marno van der Maas) * Fix interrupt status when interrupts are disabled (Marno van der Maas) * Remove go and interrupt from read registers (Marno van der Maas) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
Including: - Start address - End address - Go (hardware extended) - Epoch - Interrupt status (hardware extended) - Interrupt enable
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Thanks @marnovandermaas
We can address the potential testing extension in a follow up PR. For sunburst-chip we'll need to do a more in-depth test anyway so perhaps not worth spending time on this now.
| bnez t2, fail | ||
| li t2, 1 | ||
| csw t2, 20(ct1) // Enable interrupts | ||
| csw t2, 8(ct1) // Start sweep |
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Shouldn't we extend the test to ensure the revoker finishes and setup something for it to revoke? As is we're testing it doesn't report it's running if we haven't started it and that we're not immediately deadlocking the CPU by starting it off.
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Yes, at the moment I am running this test in simulation and checking the waveform to see if it does what I expect. Let me see if I can extend this a bit so that it at least tests something in case no-one looks at the waveform.
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I've at least checked the interrupt status now, but I agree we should probably add an actual revocation in here.
Implements the core logic of revocation control, mimicking the one found in CHERIoT Safe but then using the registers generated by reggen.
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I've fixed the revocation control interrupt output, it wasn't working properly before. The CHERIoT RTOS test suite passes with these latest changes as well. |
The hardware revoker was controlled by a memory mapped register from the CHERIoT Safe repository. This PR ports this to use reggen registers. This will make the IP more portable, specifically for the Sunburst chip repository.