rviommu: implement command queue and interrupts

machineware-gmbh · Nov 2, 2024 · 5c73c06 · 5c73c06
1 parent ae0c6f6
commit 5c73c06
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Showing 3 changed files with 314 additions and 23 deletions.
diff --git a/include/vcml/models/riscv/iommu.h b/include/vcml/models/riscv/iommu.h
@@ -98,7 +98,8 @@ class iommu : public peripheral
     static_assert(sizeof(command) == 2 * sizeof(u64), "command size");
 
     unordered_map<u64, context> m_contexts;
-    unordered_map<u64, iotlb> m_iotlb;
+    unordered_map<u64, iotlb> m_iotlb_s;
+    unordered_map<u64, iotlb> m_iotlb_g;
 
     u32 m_work;
     sc_event m_workev;
@@ -141,7 +142,7 @@ class iommu : public peripheral
                    iotlb& entry);
 
     void report_fault(const fault& req);
-    void report_irq(u32 irqid);
+    void send_msi(u32 ipsr);
 
     void restart_counter(u64 val);
     void increment_counter(context& ctx, u32 event);
@@ -154,6 +155,7 @@ class iommu : public peripheral
     void write_ddtp(u64 val);
     void write_cqt(u32 val);
     void write_cqcsr(u32 val);
+    void write_ipsr(u32 val);
     void write_iocntinh(u32 val);
     void write_iohpmcycles(u64 val);
     void write_iohpmevt(u64 val, size_t idx);
@@ -171,6 +173,8 @@ class iommu : public peripheral
     void worker();
     void overflow();
 
+    void update_ipsr();
+
 public:
     property<bool> sv32;
     property<bool> sv39;