spi: fix sifive chip-select

machineware-gmbh · Aug 19, 2024 · a9103b0 · a9103b0
1 parent 9db3e0f
commit a9103b0
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Showing 2 changed files with 11 additions and 1 deletion.
diff --git a/src/vcml/models/spi/sifive.cpp b/src/vcml/models/spi/sifive.cpp
@@ -192,7 +192,7 @@ void sifive::update_cs(bool set) {
     for (size_t i = 0; i < numcs; i++) {
         if (cs.exists(i)) {
             u32 mask = bit(i);
-            cs[i] = !!(csmode & mask) ^ (i == csid && set);
+            cs[i] = !!(csdef & mask) ^ (i == csid && set);
         }
     }
 }

diff --git a/test/models/spi_sifive.cpp b/test/models/spi_sifive.cpp
@@ -99,13 +99,23 @@ class test_harness : public test_base, public spi_host
         EXPECT_FALSE(irq);
         EXPECT_OK(out.writew<u32>(ADDR_IE, 0));
 
+        // test chip-select
+        ASSERT_OK(out.writew<u32>(ADDR_CSMODE, 2));
+        ASSERT_OK(out.writew<u32>(ADDR_CSDEF, 0));
+        ASSERT_OK(out.writew<u32>(ADDR_CSID, 2));
+
         // test transmission
         ASSERT_OK(out.writew<u32>(ADDR_TXDATA, 0x4321));
         ASSERT_OK(out.writew<u32>(ADDR_TXDATA, 0x8765));
         ASSERT_EQ(mosi.num_used(), 2);
         EXPECT_EQ(mosi.pop(), 0x21);
         EXPECT_EQ(mosi.pop(), 0x65);
 
+        // check and clear chip-select
+        ASSERT_TRUE(cs);
+        ASSERT_OK(out.writew<u32>(ADDR_CSMODE, 0));
+        EXPECT_FALSE(cs);
+
         // test nothing was received
         ASSERT_OK(out.readw<u32>(ADDR_RXDATA, data));
         EXPECT_EQ(data, 0x80000000);