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/****************************************************************************** | ||
* * | ||
* Copyright (C) 2023 MachineWare GmbH * | ||
* All Rights Reserved * | ||
* * | ||
* This is work is licensed under the terms described in the LICENSE file * | ||
* found in the root directory of this source tree. * | ||
* * | ||
******************************************************************************/ | ||
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#ifndef VCML_ARM_GICV2M_H | ||
#define VCML_ARM_GICV2M_H | ||
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#include "vcml/core/types.h" | ||
#include "vcml/core/systemc.h" | ||
#include "vcml/core/range.h" | ||
#include "vcml/core/model.h" | ||
#include "vcml/core/peripheral.h" | ||
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#include "vcml/protocols/tlm.h" | ||
#include "vcml/protocols/gpio.h" | ||
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namespace vcml { | ||
namespace arm { | ||
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class gicv2m : public peripheral | ||
{ | ||
private: | ||
void write_setspi(u32 val); | ||
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u32 read_typer(); | ||
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// disabled | ||
gicv2m(); | ||
gicv2m(const gicv2m&); | ||
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public: | ||
enum gicv2m_consts : size_t { | ||
PROD_ID = 'M', | ||
ARCH_VER = 0, | ||
IMPLEMENTER = 0, | ||
}; | ||
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enum reg_addr : size_t { | ||
TYPER_ADDR = 0x008, | ||
SETSPI_ADDR = 0x040, | ||
IIDR_ADDR = 0xfcc, | ||
}; | ||
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property<size_t> base_spi; | ||
property<size_t> num_spi; | ||
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typedef field<16, 10> TYPER_BASE_SPI; | ||
typedef field<0, 10> TYPER_NUM_SPI; | ||
typedef field<0, 10> SETSPI_SPI; | ||
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reg<u32> typer; // MSI Type register | ||
reg<u32> setspi; // Set SPI register | ||
reg<u32> iidr; // Interface Identification register | ||
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gpio_initiator_array out; | ||
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tlm_target_socket in; | ||
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gicv2m(const sc_module_name& nm); | ||
virtual ~gicv2m(); | ||
VCML_KIND(arm::gicv2m); | ||
}; | ||
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} // namespace arm | ||
} // namespace vcml | ||
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#endif |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,59 @@ | ||
/****************************************************************************** | ||
* * | ||
* Copyright (C) 2023 MachineWare GmbH * | ||
* All Rights Reserved * | ||
* * | ||
* This is work is licensed under the terms described in the LICENSE file * | ||
* found in the root directory of this source tree. * | ||
* * | ||
******************************************************************************/ | ||
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#include "vcml/models/arm/gicv2m.h" | ||
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namespace vcml { | ||
namespace arm { | ||
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void gicv2m::write_setspi(u32 val) { | ||
val &= SETSPI_SPI::MASK; | ||
if (val >= base_spi && val < base_spi + num_spi) | ||
out[val].pulse(); | ||
} | ||
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u32 gicv2m::read_typer() { | ||
return TYPER_BASE_SPI::set(base_spi) | TYPER_NUM_SPI::set(num_spi); | ||
} | ||
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gicv2m::gicv2m(const sc_module_name& nm): | ||
peripheral(nm), | ||
base_spi("base_spi", 64), | ||
num_spi("num_spi", 64), | ||
typer("typer", TYPER_ADDR), | ||
setspi("setspi", SETSPI_ADDR), | ||
iidr("iidr", IIDR_ADDR, PROD_ID << 20 | ARCH_VER << 16 | IMPLEMENTER), | ||
out("out"), | ||
in("in") { | ||
if (base_spi > TYPER_BASE_SPI()) | ||
VCML_ERROR("base_spi property out of range: %zu", base_spi.get()); | ||
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if (num_spi > TYPER_NUM_SPI()) | ||
VCML_ERROR("num_spi property out of range: %zu", num_spi.get()); | ||
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typer.allow_read_only(); | ||
typer.on_read(&gicv2m::read_typer); | ||
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setspi.allow_write_only(); | ||
setspi.on_write(&gicv2m::write_setspi); | ||
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iidr.allow_read_only(); | ||
} | ||
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gicv2m::~gicv2m() { | ||
// nothing to do | ||
} | ||
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VCML_EXPORT_MODEL(vcml::arm::gicv2m, name, args) { | ||
return new gicv2m(name); | ||
} | ||
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} // namespace arm | ||
} // namespace vcml |
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