DExx-vd_isl is advanced video digitizer add-on module for a number of Terasic FPGA development boards. It has been initially used as a development board for OSSC Pro scan converter but over time has been tailored towards a standalone product. Please check the wikipage for more information on usage and latest features.
PCB and firmware of the project are open-source except for certain Intel VIP modules which are planned to be replaced by custom implementations over time. For most parts RTL and SW are derived from OSSC Pro project with only small amount of adaptation code for the supported development boards.
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Hardware
- DExx-vd_isl module and compatible development board
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Software
- Altera Quartus Prime + device support files for target FPGA family (v 21.1 or higher - free Lite Edition suffices)
- Make
- Load the project (board/<board>/<boardname>.qpf) in Quartus
- Generate QSYS output files (only needed before first compilation or when QSYS structure has been modified)
- Open Platform Designer (Tools -> Platform Designer)
- Load platform configuration (sys.qsys)
- Generate output (Generate -> Generate HDL, Generate)
- Close Platform Designer
- Build software image if not yet done so that it becomes part of the bitstream (see next section)
- Generate the FPGA bitstream (Processing -> Start Compilation)
- Ensure that there are no major timing violations by looking into Timing Analyzer report
NOTE: If the software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) was not up to date at the time of compilation, bitstream can be quickly rebuilt with updated hex by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
NOTE2: Without Intel VIP license it's only possible to generate a time limited bitstream which needs connection to USB Blaster during use. VIP modules can be excluded by commenting out the "VIP" define from both top-level RTL and sysconfig.h in which case scaler mode is disabled.
- Generate software BSP (first-time only)
cd board/<board>/software/sys_controller_bsp
nios2-bsp-generate-files --settings=settings.bsp --bsp-dir=.
- Enter software root directory:
cd board/<board>/software/sys_controller
- Build SW for target configuration:
make [OPTIONS] [TARGET]
OPTIONS may include following definitions:
- APP_CFLAGS_DEFINED_SYMBOLS="-DDEBUG" (debug message are printed to stdout connected to JTAG UART, shown via nios2-terminal)
TARGET is typically one of the following:
- all (Default target. Compiles an ELF file)
- mem_init_generate (Generates a memory initialization file required for bitstream)
- clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations)
- Optionally test updated SW by directly downloading memory image to block RAM via JTAG (with DE10-Nano TCK needs to be reduced, see board specific notes)
nios2-download sys_controller.elf --go
Depending on target platform, bitstream can be either stored into serial flash chip or SD card where it is automatically loaded every time FPGA is subsequently powered on.
To program flash on compatible boards, FPGA configuration file must be first converted into JTAG indirect Configuration file (.jic). Open conversion tool ("File->Convert Programming Files") in Quartus, click "Open Conversion Setup Data", select "ossc.cof" and press Generate. Then open Programmer, add generated file (output_files/.jic) and press Start after which flash is programmed. Installed/updated firmware is activated after power-cycling the board.
See board specific notes for building a SD card image containing the bitstream.
- Rebuild the software in debug mode:
make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" mem_init_generate
- Download memory image via JTAG and open terminal for UART
nios2-download sys_controller.elf --go && nios2-terminal
Remember to close nios2-terminal after debug session, otherwise any JTAG transactions will hang/fail.