Add old articles

config.toml

@@ -7,14 +7,18 @@ generate_feeds = true
 build_search_index = true
 
 default_language = "en"
+taxonomies = [{ name = "tags", feed = true }]
 
 [markdown]
 highlight_code = true
 
+[search]
+index_format = "elasticlunr_json"
+
 [extra]
 default_theme = "light"
 primary_color = "#386C01"
-primary_color_alpha = "rgb(204 0 0 / 0.2)"
+primary_color_alpha = "rgb(56 108 1 / 0.2)"
 katex = true
 
 [extra.nav]

content/_index.md

@@ -3,6 +3,7 @@
 +++
 About me
 ===
+
 I am a 21 years old engineering student at Bordeaux's [ENSEIRB-MATMECA](https://www.bordeaux-inp.fr/en). I study analogue and digital electronics, signal processing and automation. My best liked subjects are FPGA programming and microelectronics. I am currently doing an internship with the CNRS at the University of Lille. The main goal of this internship is to create a RISC V instruction set in order to study memory contention on multicore SoCs.
 
 I intend to use this website as a portfolio. I will publish articles about what I study in practical work on the blog section. This should help my understanding of the subjects.

content/blog/PLL/index.md

@@ -7,7 +7,10 @@ date = 2023-03-19
 A PLL is an electronic circuit that can be used to generate an output signal that is synchronized in frequency and phase with an input signal.
 The main function of a PLL is to track and synchronize the frequency and phase of a reference signal with an output signal.
 
-![Phase Locked Loop](/assets/images/pll.svg "Analog phase locked loop"){: width = 250px}
+<figure>
+{{ image(url="pll.svg", alt="Analog phase locked loop" no_hover=true transparent=true) }}
+<figcaption>Analog phase locked loop</figcaption>
+</figure>
 
 Phase Detector
 ==============

content/blog/pokemon-silicium/index.md

@@ -0,0 +1,31 @@
++++
+authors = ["Maxime Letemple"]
+title = "Pokémon Silicium"
+date = 2022-12-10
+description = "Pokémon silicium is a simulation of a player versus player pokémon fight on FPGA."
+[taxonomies]
+tags = ["digital electronics", "school projects"]
+[extra]
+featured = true
++++
+Pokémon silicium is a simulation of a player versus player pokémon fight on FPGA. The output is a 256*160 display using VGA. The game is controlled by the [PMOD joystick from Digilent](https://digilent.com/reference/pmod/pmodjstk/start). This was a team project in order to validate my S7 at my engineering school.
+
+VHDL implementation
+===
+
+The description of the architecture is written exclusively in VHDL. We worked as a two person team. My partner wrote the game logic (managing life registers, game loop, type table, etc ...). My job was to convert the serial bus received by the joystick, to send him the inputs in the correct format and to receive informations on the status of the game in order to display them. I had to manage sprite superpostion and transparency, VGA display to create a fluid and viable interface.
+
+Converting pictures to ROM
+===
+
+In order to display sprites, I had to convert .ppm files in a 8 bits ROM written in VHDL. I wrote a programm in C that takes several pictures and convert them in one ROM. It also creates a log file, which is useful when looking for an adress.
+
+```console
+./a.out img ROM_img.vhd ronflex_back.ppm ronflex_front.ppm mew_back.ppm mew_front.ppm rayquaza_back.ppm rayquaza_front.ppm torterra_back.ppm torterra_front.ppm brasegali_back.ppm brasegali_front.ppm pikachu_back.ppm pikachu_front.ppm ectoplasma_back.ppm ectoplasma_front.ppm tiplouf_back.ppm tiplouf_front.ppm
+```
+
+More infos
+===
+
+- Resources and project code can be found [here](https://github.com/maxletemple/pokemon_silicium).
+- Download the report [here](pokemon_silicium.pdf) (in french).

content/blog/riscv-processor/index.md

@@ -0,0 +1,12 @@
++++
+authors = ["Maxime Letemple"]
+title = "RISCV-EIRB"
+date = 2023-05-23
+description = "RV32I RISCV processor from scratch"
++++
+My biggest project during my S8 was the implementation of a RV32I RISCV processor on a Nexys A7 FPGA board. I was in a team of six students, and my job was to create test binaries in order to validate each instruction. When the processor was done, I had to set the gcc toolchain to work on our processor.
+
+More infos
+===
+
+The code can be found on the [github repository](https://github.com/maxletemple/riscv_eirb).