Skip to content

Commit

Permalink
Update to v2.0.0 (#3)
Browse files Browse the repository at this point in the history
* Update to v1.0.1

* Visual improvements (#1)

* Update silkscreen
* consistent fonts
* Add castellated pads
* Remove gerber folder

* Update readme with 1.0.2 image

* Update LCSC Part numbers

* Use SOT123 for diode. Add lcsc part number. Use vbus_ff for vdd

* Add v2.0.0

Co-authored-by: Quentin <qlebastard@gmail.com>
  • Loading branch information
megamind4089 and bstiq authored Aug 8, 2022
1 parent a4c398e commit 9a0c5d4
Show file tree
Hide file tree
Showing 33 changed files with 7,445 additions and 129,216 deletions.
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -25,3 +25,4 @@ _autosave-*
*.csv
stemcell-backups/*
jlcpcb/
gerbers/
113 changes: 4 additions & 109 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

* Pro micro footprint
* STM32F4x1 series MCU
* Two layer PCB
* Support half duplex USART communication in any of D0, D1, D2, D3 using jumpers
* Onboard switch to enable/disable USB DFU bootloader
* Inbuilt TX pullup for UART half duplex communication
Expand All @@ -15,117 +16,11 @@
* JLCPCB assembly supported


> WARNING:
> This design does not have any fuse, esd protection or reverse voltage protection.
## v1.0.0

<p align="center">
<img alt="Front" src="images/v1.0.0_front.png" width="45%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="Back" src="images/v1.0.0_back.png" width="45%">
</p>

## In Real Life

<p align="center">
<img alt="irl1" src="images/v1.0.0_irl2.jpeg" width="30%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="irl2" src="images/v1.0.0_irl1.jpeg" width="60%">
</p>


#### Order it here:

v0.0.2
https://oshpark.com/shared_projects/LJiMLzWF


## Working:

* Voltage regulator
* User LED
* All pinouts
* I2C - with OLED
* UART - Split communication
* UART Half duplex on D0, D1, D2, D3
* VUSB sense

## UnTested:

* With RGB lights


## Changelog:

### v1.0.0

* Change all components to 0402 for easier routing and jlcpcb manu
* Added Boot0 switch for easier USB bootloader access
* Assembled in JLCPCB

### v0.1.0

* Silk screen update to v0.1.0
* Use 4.7k/10k for VBUS sense resistor bridge. Changed after testing

### v0.0.2

* Added VBUS Sense
* Removed SWD breakout
* Added extra pinout at bottom like elite C

### v0.0.1

* Initial revision
* 0602 SMD components
* SWD breakout at bottom


## Previous versions:

### v0.1.0

<p align="center">
<img alt="Front" src="images/v0.1.0_front.png" width="45%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="Back" src="images/v0.1.0_back.png" width="45%">
</p>


### v0.0.2

<p align="center">
<img alt="Front" src="images/v0.0.2_front.png" width="45%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="Back" src="images/v0.0.2_back.png" width="45%">
</p>


#### In Real Life
## v2.0.0

<p align="center">
<img alt="irl1" src="images/v0.0.2_irl1.jpg" width="45%">
<img alt="front" src="images/front.png" width="45%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="irl2" src="images/v0.0.2_irl2.jpg" width="45%">
<img alt="back" src="images/back.png" width="45%">
</p>


### v0.0.1

<p align="center">
<img alt="Front" src="images/v0.0.1_front.png" width="45%">
&nbsp; &nbsp; &nbsp; &nbsp;
<img alt="Back" src="images/v0.0.1_back.png" width="45%">
</p>

> ** Warning:**
> Current version might be not tested yet

Pictures are generated using pcbdraw:

```
pcbdraw --dpi 1024 -s set-blue-enig -l lib\pcbdraw_footprints\,default stemcell.kicad_pcb images\v1.0.0_front.png
pcbdraw --dpi 1024 -s set-blue-enig -l lib\pcbdraw_footprints\,default -b stemcell.kicad_pcb images\v1.0.0_back.png
```
Loading

0 comments on commit 9a0c5d4

Please sign in to comment.