Verilog

Overview

This repository contains codes and reports written for Digital Design class in Fall, 2020.

Please note that reports were not reviewed by anyone, so please cite reports at your own risk.

Contents

Class covered following topics:

• week 3: AND, OR gates
• week 4: NAND, NOR, XOR gates
• week 5: De Morgan's Law
• week 6: Adder, Subtractor
• week 7: Parity bit checker, Comparator
• week 8: Seven Segment Display
• week 9: Encoder, Decoder
• week 10: N-bit Adder, Subtractor
• week 11: Filpflop
• week 12: Counter
• week 13: Ring, Updown Counter

References

References used are written in each report but following references are the one that I highly cited.

• 강석태, “Verilog HDL Summary”, http://vlsi.hongik.ac.kr/lecture/%EC%8B%A4%ED%97%98/Verilog_Summary.pdf.
• 장영조, “디지털공학 및 실습 강의자료”, https://cms3.koreatech.ac.kr/yjjang/1827/subview.do.
• 장영조, “디지털 시스템설계 및 실습 강의자료”,https://cms3.koreatech.ac.kr/yjjang/1816/subview.do.