Reformat to LLVM-style formatting

.clang-format

@@ -1,61 +1,2 @@
-Language: Cpp
-# BasedOnStyle: Chromium
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignConsecutiveAssignments: false
-AlignConsecutiveDeclarations: false
-AlignEscapedNewlinesLeft: true
-AlignOperands: true
-AlignTrailingComments: true
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: false
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: Inline
-AllowShortIfStatementsOnASingleLine: false
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: true
-AlwaysBreakTemplateDeclarations: true
-BinPackArguments: true
-BinPackParameters: true
-BreakBeforeBinaryOperators: None
-BreakBeforeBraces: Attach
-BreakBeforeTernaryOperators: true
-BreakConstructorInitializersBeforeComma: false
-BreakStringLiterals: true
-ColumnLimit: 120
-ConstructorInitializerAllOnOneLineOrOnePerLine: true
-ConstructorInitializerIndentWidth: 4
-ContinuationIndentWidth: 4
-Cpp11BracedListStyle: true
-ExperimentalAutoDetectBinPacking: false
-IncludeCategories: 
- - Regex: '^<.*\.h>'
- Priority: 1
- - Regex: '^<.*'
- Priority: 2
- - Regex: '.*'
- Priority: 3
-IndentCaseLabels: true
-IndentWidth: 4
-IndentWrappedFunctionNames: false
-KeepEmptyLinesAtTheStartOfBlocks: false
-MaxEmptyLinesToKeep: 1
-PenaltyBreakBeforeFirstCallParameter: 1
-PointerAlignment: Left
-ReflowComments: true
-SortIncludes: true
-SpaceAfterCStyleCast: false
-SpaceBeforeAssignmentOperators: true
-SpaceBeforeParens: ControlStatements
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 2
-SpacesInAngles: false
-SpacesInContainerLiterals: true
-SpacesInCStyleCastParentheses: false
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard: Cpp11
-TabWidth: 4
-UseTab: Never
+BasedOnStyle: LLVM
+AlwaysBreakTemplateDeclarations: Yes

components/vsrtl_adderandreg.h

@@ -11,27 +11,27 @@ namespace core {
 
 class AdderAndReg : public Design {
 public:
-  AdderAndReg() : Design("Adder and Register") {
-  // Connect objects
-  4 >> adder->op1;
-  reg->out >> adder->op2;
-  adder->out >> reg->in;
-  }
-  static constexpr int m_cVal = 4;
+ AdderAndReg() : Design("Adder and Register") {
+ // Connect objects
+ 4 >> adder->op1;
+ reg->out >> adder->op2;
+ adder->out >> reg->in;
+ }
+ static constexpr int m_cVal = 4;
 
-  // Create objects
-  SUBCOMPONENT(adder, Adder<32>);
-  SUBCOMPONENT(reg, Register<32>);
+ // Create objects
+ SUBCOMPONENT(adder, Adder<32>);
+ SUBCOMPONENT(reg, Register<32>);
 
-  PARAMETER(a, int, 1);
-  PARAMETER(b, std::string, "abc");
-  PARAMETER(c, bool, true);
-  /*
- PARAMETER(d, std::vector<int>, 123);
- PARAMETER(e, std::vector<std::string>, TYPE({"abc", "def", "eh"}));
- */
+ PARAMETER(a, int, 1);
+ PARAMETER(b, std::string, "abc");
+ PARAMETER(c, bool, true);
+ /*
+PARAMETER(d, std::vector<int>, 123);
+PARAMETER(e, std::vector<std::string>, TYPE({"abc", "def", "eh"}));
+*/
 };
 
-}  // namespace core
-}  // namespace vsrtl
-#endif  // VSRTL_ADDERANDREG_H
+} // namespace core
+} // namespace vsrtl
+#endif // VSRTL_ADDERANDREG_H

components/vsrtl_aluandreg.h

@@ -13,19 +13,19 @@ namespace core {
 
 class ALUAndReg : public Design {
 public:
-  ALUAndReg() : Design("ALU and Register") {
-  // Connect objects
-  4 >> alu->op1;
-  reg->out >> alu->op2;
-  ALU_OPCODE::ADD >> alu->ctrl;
-  alu->out >> reg->in;
-  }
-  static constexpr int m_cVal = 4;
+ ALUAndReg() : Design("ALU and Register") {
+ // Connect objects
+ 4 >> alu->op1;
+ reg->out >> alu->op2;
+ ALU_OPCODE::ADD >> alu->ctrl;
+ alu->out >> reg->in;
+ }
+ static constexpr int m_cVal = 4;
 
-  // Create objects
-  SUBCOMPONENT(alu, ALU<32>);
-  SUBCOMPONENT(reg, Register<32>);
+ // Create objects
+ SUBCOMPONENT(alu, ALU<32>);
+ SUBCOMPONENT(reg, Register<32>);
 };
 
-}  // namespace core
-}  // namespace vsrtl
+} // namespace core
+} // namespace vsrtl

components/vsrtl_counter.h

@@ -13,35 +13,36 @@ namespace core {
 
 template <unsigned int width>
 class Counter : public Design {
- static_assert((sizeof(VSRTL_VT_U) * CHAR_BIT) >= width, "Counter width greater than VSRTL valuetype width");
+ static_assert((sizeof(VSRTL_VT_U) * CHAR_BIT) >= width,
+ "Counter width greater than VSRTL valuetype width");
 
 public:
- Counter() : Design(std::to_string(width) + " bit counter") {
- // Connect
- 0 >> adders[0]->Cin;
- 1 >> adders[0]->A;
- regs[0]->out >> adders[0]->B;
- regs[0]->out >> *value->in[0];
- adders[0]->S >> regs[0]->in;
-
- for (unsigned i = 1; i < width; i++) {
- adders[i - 1]->Cout >> adders[i]->Cin;
- regs[i]->out >> adders[i]->A;
- regs[i]->out >> *value->in[i];
- 0 >> adders[i]->B;
- adders[i]->S >> regs[i]->in;
- }
-
- value->out >> outputReg->in;
+ Counter() : Design(std::to_string(width) + " bit counter") {
+ // Connect
+ 0 >> adders[0]->Cin;
+ 1 >> adders[0]->A;
+ regs[0]->out >> adders[0]->B;
+ regs[0]->out >> *value->in[0];
+ adders[0]->S >> regs[0]->in;
+
+ for (unsigned i = 1; i < width; i++) {
+ adders[i - 1]->Cout >> adders[i]->Cin;
+ regs[i]->out >> adders[i]->A;
+ regs[i]->out >> *value->in[i];
+ 0 >> adders[i]->B;
+ adders[i]->S >> regs[i]->in;
  }
 
- SUBCOMPONENTS(adders, FullAdder, width);
- SUBCOMPONENTS(regs, Register<1>, width);
- SUBCOMPONENT(outputReg, Register<width>);
- SUBCOMPONENT(value, Collator<width>);
+ value->out >> outputReg->in;
+ }
+
+ SUBCOMPONENTS(adders, FullAdder, width);
+ SUBCOMPONENTS(regs, Register<1>, width);
+ SUBCOMPONENT(outputReg, Register<width>);
+ SUBCOMPONENT(value, Collator<width>);
 };
 
-}  // namespace core
-}  // namespace vsrtl
+} // namespace core
+} // namespace vsrtl
 
-#endif  // VSRTL_NBITADDER_H
+#endif // VSRTL_NBITADDER_H

components/vsrtl_enumandmux.h

@@ -14,36 +14,36 @@ Enum(TestEnum, A, B, C, D, E, F);
 
 class EnumAndMux : public Design {
 public:
-  EnumAndMux() : Design("Enum and Multiplexer") {
-  // Connect objects
-  1 >> mux->get(TestEnum::A);
-  2 >> mux->get(TestEnum::B);
-  3 >> mux->get(TestEnum::E);
-  0xDEADBEEF >> mux->others();
-
-  reg->out >> mux->select;
-
-  1 >> adder->op1;
-  reg->out >> adder->op2;
-
-  (TestEnum::_size() - 1) >> cmp->op1;
-  reg->out >> cmp->op2;
-
-  // Register next-state input mux
-  cmp->out >> regIn_mux->select;
-  0 >> *regIn_mux->ins[1];
-  adder->out >> *regIn_mux->ins[0];
-  regIn_mux->out >> reg->in;
-  }
-  static constexpr int width = 32;
-
-  // Create objects
-  SUBCOMPONENT(mux, TYPE(EnumMultiplexer<TestEnum, width>));
-  SUBCOMPONENT(adder, Adder<TestEnum::width()>);
-  SUBCOMPONENT(reg, Register<TestEnum::width()>);
-  SUBCOMPONENT(regIn_mux, TYPE(Multiplexer<2, TestEnum::width()>));
-  SUBCOMPONENT(cmp, Eq<TestEnum::width()>);
+ EnumAndMux() : Design("Enum and Multiplexer") {
+ // Connect objects
+ 1 >> mux->get(TestEnum::A);
+ 2 >> mux->get(TestEnum::B);
+ 3 >> mux->get(TestEnum::E);
+ 0xDEADBEEF >> mux->others();
+
+ reg->out >> mux->select;
+
+ 1 >> adder->op1;
+ reg->out >> adder->op2;
+
+ (TestEnum::_size() - 1) >> cmp->op1;
+ reg->out >> cmp->op2;
+
+ // Register next-state input mux
+ cmp->out >> regIn_mux->select;
+ 0 >> *regIn_mux->ins[1];
+ adder->out >> *regIn_mux->ins[0];
+ regIn_mux->out >> reg->in;
+ }
+ static constexpr int width = 32;
+
+ // Create objects
+ SUBCOMPONENT(mux, TYPE(EnumMultiplexer<TestEnum, width>));
+ SUBCOMPONENT(adder, Adder<TestEnum::width()>);
+ SUBCOMPONENT(reg, Register<TestEnum::width()>);
+ SUBCOMPONENT(regIn_mux, TYPE(Multiplexer<2, TestEnum::width()>));
+ SUBCOMPONENT(cmp, Eq<TestEnum::width()>);
 };
 
-}  // namespace core
-}  // namespace vsrtl
+} // namespace core
+} // namespace vsrtl

components/vsrtl_fulladder.h

@@ -9,41 +9,42 @@ namespace core {
 
 class FullAdder : public Component {
 public:
- FullAdder(const std::string& name, SimComponent* parent) : Component(name, parent) {
- A >> *xor1->in[0];
- B >> *xor1->in[1];
+ FullAdder(const std::string &name, SimComponent *parent)
+ : Component(name, parent) {
+ A >> *xor1->in[0];
+ B >> *xor1->in[1];
 
-  xor1->out >> *xor2->in[0];
-  Cin >> *xor2->in[1];
+ xor1->out >> *xor2->in[0];
+ Cin >> *xor2->in[1];
 
-  xor1->out >> *and1->in[0];
-  Cin >> *and1->in[1];
+ xor1->out >> *and1->in[0];
+ Cin >> *and1->in[1];
 
-  A >> *and2->in[0];
-  B >> *and2->in[1];
+ A >> *and2->in[0];
+ B >> *and2->in[1];
 
-  and1->out >> *or1->in[0];
-  and2->out >> *or1->in[1];
+ and1->out >> *or1->in[0];
+ and2->out >> *or1->in[1];
 
-  or1->out >> Cout;
-  xor2->out >> S;
-  }
+ or1->out >> Cout;
+ xor2->out >> S;
+ }
 
-  INPUTPORT(A, 1);
-  INPUTPORT(B, 1);
-  INPUTPORT(Cin, 1);
+ INPUTPORT(A, 1);
+ INPUTPORT(B, 1);
+ INPUTPORT(Cin, 1);
 
-  OUTPUTPORT(S, 1);
-  OUTPUTPORT(Cout, 1);
+ OUTPUTPORT(S, 1);
+ OUTPUTPORT(Cout, 1);
 
-  SUBCOMPONENT(xor1, TYPE(Xor<1, 2>));
-  SUBCOMPONENT(xor2, TYPE(Xor<1, 2>));
-  SUBCOMPONENT(and1, TYPE(And<1, 2>));
-  SUBCOMPONENT(and2, TYPE(And<1, 2>));
-  SUBCOMPONENT(or1, TYPE(Or<1, 2>));
+ SUBCOMPONENT(xor1, TYPE(Xor<1, 2>));
+ SUBCOMPONENT(xor2, TYPE(Xor<1, 2>));
+ SUBCOMPONENT(and1, TYPE(And<1, 2>));
+ SUBCOMPONENT(and2, TYPE(And<1, 2>));
+ SUBCOMPONENT(or1, TYPE(Or<1, 2>));
 };
 
-}  // namespace core
-}  // namespace vsrtl
+} // namespace core
+} // namespace vsrtl
 
-#endif  // VSRTL_FULLADDER_H
+#endif // VSRTL_FULLADDER_H