[experimental-tmp4] Support to boot all cpus for msm8994/2

[fekz115]

• refactored and documented fdt-related functions in cpu-boot.c(but seems still ugly for my taste).
• used Doxygen documentation format. I think it is still readable and no reason to remove it even if nobody wants to follow it.
• rewritten functions msm_spm_turn_on_cpu_rail, power_on_l2_cache_msm8994, cpu_boot_cortex_a_msm8994 in separate file.
  Now my dmesg seems like with all CPUs enabled:
  https://gist.github.com/fekz115/50c2ae33149d62adb791ac0dd9813a3f

[    0.014306] smp: Bringing up secondary CPUs ...
[    0.015839] Detected VIPT I-cache on CPU1
[    0.016206] CPU1: Booted secondary processor 0x0000000001 [0x410fd033]
[    0.017963] Detected VIPT I-cache on CPU2
[    0.018104] CPU2: Booted secondary processor 0x0000000002 [0x410fd033]
[    0.019189] Detected VIPT I-cache on CPU3
[    0.019277] CPU3: Booted secondary processor 0x0000000003 [0x410fd033]
[    0.020963] CPU features: detected: Spectre-v2
[    0.021301] CPU features: detected: Spectre-v3a
[    0.021498] CPU features: detected: Spectre-v4
[    0.021661] CPU features: detected: Spectre-BHB
[    0.021866] CPU features: detected: ARM erratum 834220
[    0.022045] CPU features: detected: ARM erratum 1742098
[    0.022239] CPU features: detected: ARM erratum 832075
[    0.022422] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.022596] Detected PIPT I-cache on CPU4
[    0.024258] CPU4: Booted secondary processor 0x0000000100 [0x411fd072]
[    0.028912] Detected PIPT I-cache on CPU5
[    0.030579] CPU5: Booted secondary processor 0x0000000101 [0x411fd072]
[    0.033153] smp: Brought up 1 node, 6 CPUs
[    0.033530] SMP: Total of 6 processors activated.
[    0.033555] CPU features: detected: 32-bit EL0 Support
[    0.033574] CPU features: detected: 32-bit EL1 Support
[    0.033603] CPU features: detected: CRC32 instructions
[    0.034977] CPU: All CPU(s) started at EL1

[fekz115]

Updates:

• converted Doxygen to Kerneldoc (still think Doxygen is better)
• hardcoded values to enable cores in lk2nd/smp/gpl/cortex-a-msm8994.c (as adviced minecrell, because it will be hard to send it to upstream)
• removed fdt functions refactoring as they are not needed anymore for this feature
• rebased on experimental-tmp4 branch (hope it's actual)

It still boots all cpus:

• dmesg without it: https://gist.github.com/fekz115/88c7c1b31ade24250cf46fff4e660fe6
• dmesg with it: https://gist.github.com/fekz115/1a58785fbcdfd37c52e808c4067c470a
  But, unfortunately, it seems like somewhere in kernel regulators code race condition, so, still not booted to OS...

Needed kernel changes:

• fekz115/linux@9c60c39

[FuchtelJockel]

I can confirm this patch to work on a LG G4.

The main boot path has broken PSCI. Booting the phone from fastboot reboot works for some reason.

Spin-Table CPUs dmesg:

[    0.013844] smp: Bringing up secondary CPUs ...
[    0.015317] Detected VIPT I-cache on CPU1
[    0.015832] CPU1: Booted secondary processor 0x0000000001 [0x410fd033]
[    0.017706] Detected VIPT I-cache on CPU2
[    0.017926] CPU2: Booted secondary processor 0x0000000002 [0x410fd033]
[    0.019064] Detected VIPT I-cache on CPU3
[    0.019202] CPU3: Booted secondary processor 0x0000000003 [0x410fd033]
[    0.020956] CPU features: detected: Spectre-v2
[    0.021293] CPU features: detected: Spectre-v3a
[    0.021478] CPU features: detected: Spectre-v4
[    0.021656] CPU features: detected: Spectre-BHB
[    0.021883] CPU features: detected: ARM erratum 1742098
[    0.022080] CPU features: detected: ARM erratum 832075
[    0.022250] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.022423] Detected PIPT I-cache on CPU4
[    0.025260] CPU4: Booted secondary processor 0x0000000100 [0x411fd072]
[    0.030510] Detected PIPT I-cache on CPU5
[    0.033389] CPU5: Booted secondary processor 0x0000000101 [0x411fd072]
[    0.036307] smp: Brought up 1 node, 6 CPUs
[    0.036653] SMP: Total of 6 processors activated.
[    0.036744] CPU: All CPU(s) started at EL1
[    0.036773] CPU features: detected: 32-bit EL0 Support
[    0.036806] CPU features: detected: CRC32 instructions

For some reason the the qcom-clk-smd-rpm clock driver fails if multiple cores get enabled.
Race condition in the driver?
This also occurred with the PSCI boot path.

Clock dmesg:

[    5.619321] qcom-clk-smd-rpm remoteproc:smd-edge:rpm-requests:clock-controller: Error registering SMD clock driver (-110)
[    5.619387] qcom-clk-smd-rpm: probe of remoteproc:smd-edge:rpm-requests:clock-controller failed with error -110

Maybe this driver should load before the CPUs get enabled?