This repo is ment to be used as public location to share code between Lime Microsystems FPGA design projects.
If you are new here then before commiting any changes or adding any new modules review: coding_guidelines
All modules should have:
- Self checking test bench
- Document with description what it does and how to use it
Here you can find summary of available modules and their status.
Status description:
- 🟡 dev - module is still under development
- 🟢 prod - module is tested and proven to be functional
| Module | Version | Status | Description |
|---|---|---|---|
| axis_fifo | v0.0 | 🟡 dev | AXI Stream FIFO implementation with dual port RAM |
| m_to_axi_lite | v0.0 | 🟡 dev | Converts general data bus with data valid signals to AXI4-Lite master interface |
| gt_channel | v0.0 | 🟡 dev | Send/receive data trough transceivers (Aurora 8b10b) |
| lms7002 | v0.0 | 🟡 dev | Top module for LMS7002M IC digital interface |
| gpio_top | v0.0 | 🟡 dev | Basic Module for GPIO control |
| rx_path_top | v0.0 | 🟡 dev | Receive and pack IQ samples into Stream packets |
| tx_path_top | v0.0 | 🟡 dev | Unpack packets into IQ samples, perform synchronisation |