Implementation of a simple 5-stage 32-bit pipelined RISC processor and its assembler using VHDL and Python
The processor in this project has a RISC-like instruction set architecture. There are eight 4-byte general purpose registers, R0, till R7. Another two general purpose registers, one works as program counter (PC) and the other works as a stack pointer (SP), and hence, points to the top of the stack. The initial value of SP is (2^11-1). The memory address space is 4 KB of 16-bit width and is word addressable. The bus between memory and the processor is 16-bit widths for instruction cache and 32-bit widths for data cache. When an interrupt occurs, the processor finishes the currently fetched instructions (instructions that have already entered the pipeline), then the address of the next instruction (in PC) is saved on top of the stack, and PC is loaded from address [2-3] of the memory (the address takes two words). To return from an interrupt, an RTI instruction loads PC from the top of stack, and the flow of the program resumes from the instruction after the interrupted instruction.
A program written in Python that compiles sample assembly programs and generate the equivalent machine code hex files to be loaded into the CPU memory.
Running:
Open a terminal in the Assembler directory, then write the following command:
./assembler.exe "<.asm file relative path>"Example:
./assembler.exe "test cases/Branch.asm"The Common directory contains components that are used in most if not all the processor stages.
Data Hazard Detection Unit:
Dynamic Branch Fetching:
Register Fetching:
Interrupt Fetching:
PC Fetching:
Control Unit Decoder:
Register File Decoder:
ALU Execution:
Branch Detection Unit:
