neelabhro / FSM-Verilog- Public

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Door Lock with provision to set the password in Real Time

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Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
FSM_mealy_10101.v		FSM_mealy_10101.v
README.md		README.md
clock_pulse.v		clock_pulse.v
cons.xdc		cons.xdc
debounce.v		debounce.v
freq_div.v		freq_div.v
top.v		top.v

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FSM-Verilog

This is a Door Lock Project designed to run on the Basys 3 Artix-7 FPGA as it is, or can be used on other FPGAs with changes in the Constraint File.

It has been coded such that the Door Lock Pattern can be set in real time using the switches already present on the Board.

The idea of a Finite State Machine (FSM) has been used to implement this