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nitindinnu/README.md
  • 👋 Hi, I’m @nitindinnu
  • 👀 I’m interested in new stuff based on VLSI
  • 🌱 I’m pro-efficient with VLSI FRONTEND RTL design and Verification (verilog,Sytem verilog,UVM)
  • 💞️ I’m looking to collaborate on Any project related to VLSI domain
  • 📫 How to reach me nitin2239@outlook.com

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