- includes the 1_wire master and a trivial 1_wire slave
- CoCoTB testbench for functional verification
- $ make
This is a short tabular description of the contents of each folder in the repo.
| Folder | Description |
|---|---|
| rtl | VHDL RTL implementation files |
| cocotb_sim | Functional Verification with CoCoTB (Python-based) |
| pyuvm_sim | Functional Verification with pyUVM (Python impl. of UVM standard) |
This is the tree view of the strcture of the repo.
. ├── rtl │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files └── pyuvm_sim ├── Makefile └── python files