doc: flpr and building for nrf54l15

Adds building article
Adds FLPR intro

Signed-off-by: Anna Wojdylo <anna.wojdylo@nordicsemi.no>

doc/nrf/app_dev/device_guides/nrf54l/building_nrf54l.rst

@@ -0,0 +1,97 @@
+.. _building_nrf54l:
+
+Building and programming with nRF54L15 DK
+#########################################
+
+This guide provides instructions on how to build and program the nRF54L15 development kit.
+Whether you are working with single or multi-image builds, the following sections will guide you through the necessary steps.
+
+Depending on the sample, you must program only the application core or both the FLPR and the application core.
+Additionally, the process will differ based on whether you are working with a single-image or multi-image build.
+
+Building for the application core
+*********************************
+
+For instructions on building for the application core only, see how to :ref:`program an application <programming_cmd>`.
+
+Building for the application and FLPR core
+******************************************
+
+This section outlines how to build and program for both the application and FLPR cores, covering separate builds and sysbuild configurations.
+
+Separate images
+---------------
+
+To build and program the application sample and the FLPR sample as separate images, follow these steps:
+
+.. tabs::
+
+ .. group-tab:: west
+
+ 1. |open_terminal_window_with_environment|
+ #. For the FLPR core, erase the flash memory and program the FLPR sample:
+
+ .. Commands TBD
+
+ .. code-block:: console
+
+ west flash --erase
+
+ #. For the application core, navigate to the build folder of the application sample and repeat the flash erase command:
+
+ .. code-block:: console
+
+ west flash --erase
+
+ .. group-tab:: nRF Util
+
+ 1. |open_terminal_window_with_environment|
+ #. For the FLPR core, run the following command to erase the flash memory of the FLPR core and program the sample:
+
+ .. Commands TBD
+
+ .. code-block:: console
+
+ nrfutil device program --firmware zephyr.hex --options chip_erase_mode=ERASE_ALL --core Network
+
+ #. For the application core, navigate to its build folder and run:
+
+ .. code-block:: console
+
+ nrfutil device program --firmware zephyr.hex --options chip_erase_mode=ERASE_ALL
+
+ .. note::
+ The application build folder will be in a sub-directory which is the name of the folder of the application
+
+ #. Reset the development kit:
+
+ .. Commands TBD
+
+ .. code-block:: console
+
+ nrfutil device reset --reset-kind=RESET_PIN
+
+ See :ref:`readback_protection_error` if you encounter an error.
+
+With sysbuild
+-------------
+
+To build and program with sysbuild, complete the following steps:
+
+.. tabs::
+
+ .. group-tab:: Using VPR Launcher
+
+ Instructions TBA
+
+ .. code-block:: console
+
+ # Example command TBD
+
+ .. group-tab:: Using application that aupports multi-image builds
+
+ Instructions TBA
+
+ .. code-block:: console
+
+ # Example command TBD

doc/nrf/app_dev/device_guides/nrf54l/index.rst

@@ -36,4 +36,6 @@ Zephyr and the |NCS| provide support and contain board definitions for developin
 
  features
  testing_dfu
+ vpr_flpr
+ building_nrf54l
  peripheral_sensor_node_shield

doc/nrf/app_dev/device_guides/nrf54l/vpr_flpr.rst

@@ -0,0 +1,35 @@
+.. _vpr_flpr_nrf54l:
+
+Working with the FLPR core
+##########################
+
+The nRF54L15 SoC has a dedicated VPR CPU (RISC-V architecture), named *fast lightweight peripheral processor* (FLPR) optimized for software-defined peripherals (SDP).
+The following peripherals are available for use with the FLPR core, and can be accessed through the appropriate Zephyr Device Driver API:
+
+* GPIO
+* GPIOTE
+* GRTC
+* TWIM
+* UARTE
+* VPR
+
+Running FLPR
+************
+
+FLPR can function as a generic core, operating under the full Zephyr kernel.
+In this configuration, building the FLPR target is similar the application core.
+However, the application core build must incorporate an overlay that enables the FLPR coprocessor.
+This ensures that the necessary code to initiate FLPR is integrated.
+
+Software Defined Peripherals
+----------------------------
+
+FLPR is optimized for implementing SDP.
+For more information, see <link tba> documentation page.
+
+Memory allocation
+*****************
+
+If a FLPR CPU is running, it can lead to increased latency when accessing ``RAM_01``.
+Because of this, when FLPR is used in a project, you should utilize ``RAM_01`` to store only the FLPR code, FLPR data, and the application CPU's non-time-sensitive information.
+Conversely, you should use ``RAM_00`` to store data with strict access time requirements such as DMA buffers, and the application CPU data used in low-latency ISRs.