o1vm/riscv32: implement sub

o1-labs · Nov 20, 2024 · 298f4cb · 298f4cb
1 parent 18aa79c
commit 298f4cb
Showing 1 changed file with 14 additions and 1 deletion.
diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs
@@ -1296,7 +1296,20 @@ pub fn interpret_rtype<Env: InterpreterEnv>(env: &mut Env, instr: RInstruction)
             env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         RInstruction::Sub => {
-            unimplemented!("Sub");
+            /* sub: x[rd] = x[rs1] - x[rs2] */
+            let local_rs1 = env.read_register(&rs1);
+            let local_rs2 = env.read_register(&rs2);
+            let underflow_scratch = env.alloc_scratch();
+            let rd_scratch = env.alloc_scratch();
+            let local_rd = unsafe {
+                let (local_rd, _underflow) =
+                    env.sub_witness(&local_rs1, &local_rs2, rd_scratch, underflow_scratch);
+                local_rd
+            };
+            env.write_register(&rd, local_rd);
+
+            env.set_instruction_pointer(next_instruction_pointer.clone());
+            env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         RInstruction::ShiftLeftLogical => {
             unimplemented!("ShiftLeftLogical");