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Merge pull request #2901 from o1-labs/dw/and-tests
o1vm/riscv32im: add tests for AND
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Original file line number | Diff line number | Diff line change |
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.section .text | ||
.globl _start | ||
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_start: | ||
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# Simple AND | ||
li t0, 0b1100 # t0 = 0b1100 | ||
li t1, 0b1010 # t1 = 0b1010 | ||
and t2, t0, t1 # t2 = t0 & t1 (Expected: t2 = 0b1000) | ||
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# AND with zero (result always zero) | ||
li t3, 0b1111 # t3 = 0b1111 | ||
li t4, 0 # t4 = 0 | ||
and t5, t3, t4 # t5 = t3 & t4 (Expected: t5 = 0) | ||
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# AND of identical values (result same value) | ||
li t6, 0b1010 # t6 = 0b1010 | ||
li t0, 0b1010 # t0 = 0b1010 | ||
and t1, t6, t0 # t1 = t6 & t0 (Expected: t1 = 0b1010) | ||
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# Custom exit syscall | ||
li a0, 0 | ||
li a1, 0 | ||
li a2, 0 | ||
li a3, 0 | ||
li a4, 0 | ||
li a5, 0 | ||
li a6, 0 | ||
li a7, 42 | ||
ecall |
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