Merge pull request #2775 from o1-labs/dw/implement-srl-riscv32

o1vm/riscv32: implement R type instruction srl
o1-labs · Nov 20, 2024 · dc49843 · dc49843
2 parents b3b62cb + 75327ec
commit dc49843
Showing 1 changed file with 11 additions and 1 deletion.
diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs
@@ -1364,7 +1364,17 @@ pub fn interpret_rtype<Env: InterpreterEnv>(env: &mut Env, instr: RInstruction)
             env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         RInstruction::ShiftRightLogical => {
-            unimplemented!("ShiftRightLogical");
+            /* srl: x[rd] = x[rs1] >> x[rs2] */
+            let local_rs1 = env.read_register(&rs1);
+            let local_rs2 = env.read_register(&rs2);
+            let local_rd = unsafe {
+                let pos = env.alloc_scratch();
+                env.shift_right(&local_rs1, &local_rs2, pos)
+            };
+            env.write_register(&rd, local_rd);
+
+            env.set_instruction_pointer(next_instruction_pointer.clone());
+            env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         RInstruction::ShiftRightArithmetic => {
             unimplemented!("ShiftRightArithmetic");