add ut #8
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add ut #8
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…nAIEval into add_ut_modeltest Signed-off-by: Wenxin Zhang <wenxin.zhang@intel.com>
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Signed-off-by: Wenxin Zhang <wenxin.zhang@intel.com>
for more information, see https://pre-commit.ci
Signed-off-by: Wenxin Zhang <wenxin.zhang@intel.com>
Signed-off-by: Wenxin Zhang <wenxin.zhang@intel.com>
hshen14
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Type of Change
add ut and model test