Merge pull request #11 from msfschaffner/master

Add cache test program, tetris binary and update riscv-pk

Makefile

@@ -96,7 +96,11 @@ pk: install-dir $(RISCV)/bin/riscv64-unknown-elf-gcc
 all: gnu-toolchain-newlib gnu-toolchain-libc fesvr isa-sim tests pk
 
 
-vmlinux: $(buildroot_defconfig) $(linux_defconfig) $(busybox_defconfig) $(RISCV)/bin/riscv64-unknown-elf-gcc $(RISCV)/bin/riscv64-unknown-linux-gnu-gcc
+cachetest: 
+	cd ./cachetest/ && $(RISCV)/bin/riscv64-unknown-elf-gcc cachetest.c -o cachetest.elf
+	cp ./cachetest/cachetest.elf rootfs/
+
+vmlinux: $(buildroot_defconfig) $(linux_defconfig) $(busybox_defconfig) $(RISCV)/bin/riscv64-unknown-elf-gcc $(RISCV)/bin/riscv64-unknown-linux-gnu-gcc cachetest
 	mkdir -p build
 	make -C buildroot clean
 	make -C buildroot defconfig BR2_DEFCONFIG=../configs/buildroot_defconfig
@@ -113,14 +117,16 @@ bbl_binary: bbl
 	riscv64-unknown-elf-objcopy -O binary bbl bbl_binary
 
 clean: 
-	rm -rf vmlinux bbl riscv-pk/build/vmlinux riscv-pk/build/bbl
+	rm -rf vmlinux bbl riscv-pk/build/vmlinux riscv-pk/build/bbl cachetest/*.elf
 	make -C buildroot distclean
 
 bbl.bin: bbl
 	riscv64-unknown-elf-objcopy -S -O binary --change-addresses -0x80000000 $< $@
 
 clean-all: clean
-	rm -rf riscv-fesvr/build riscv-isa-sim/build riscv-gnu-toolchain/build riscv-tests/build riscv-pk/build
+	rm -rf riscv-fesvr/build riscv-isa-sim/build riscv-gnu-toolchain/build riscv-tests/build riscv-pk/build cachetest/*.elf
+
+.PHONY: cachetest
 
 help:
 	@echo "usage: $(MAKE) [RISCV='<install/here>'] [tool/img] ..."

cachetest/cachetest.c

@@ -0,0 +1,59 @@
+// Copyright 2019 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+extern int printf(const char *format, ...);
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+char buffer[1024 * 1024];
+
+void sweep(int stride)
+{
+  long instret_start, cycle_start;
+  int max_j = 4 * 1024;
+  int working_set = max_j * stride;
+
+  for(int i = 0; i < 10; i++)
+  {
+    if(i == 1)
+    {
+      instret_start = read_csr(instret);
+      cycle_start = read_csr(cycle);
+    }
+
+    for(int j = 0; j < max_j; j += 4)
+    {
+      buffer[(j + 0) * stride] = 0;
+      buffer[(j + 1) * stride] = 0;
+      buffer[(j + 2) * stride] = 0;
+      buffer[(j + 3) * stride] = 0;
+    }
+  }
+
+  long instrets = read_csr(instret) - instret_start;
+  long cycles = read_csr(cycle) - cycle_start;
+
+  printf("working_set = %2dKB, %ld instructions, %ld cycles, CPI = %f\n", 
+         working_set / 1024, instrets, cycles, (float) cycles / instrets);
+}
+
+int main()
+{
+  sweep(0);
+  sweep(1);
+  sweep(2);
+  sweep(4);
+  sweep(8);
+  sweep(16);
+
+  return 0;
+}