fixes2

openhwgroup · Dec 11, 2024 · c36df2d · c36df2d
1 parent cdb62ec
commit c36df2d
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Showing 5 changed files with 13 additions and 14 deletions.
diff --git a/core/compressed_decoder.sv b/core/compressed_decoder.sv
@@ -44,7 +44,7 @@ module compressed_decoder #(
     is_compressed_o  = 1'b1;
     instr_o          = instr_i;
     is_macro_instr_o = 0;
-    is_zcmt_instr_o  = 0;
+    is_zcmt_instr_o  = 1'b0;;
 
     // I: |    imm[11:0]    | rs1 | funct3 |    rd    | opcode |
     // S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
@@ -875,7 +875,7 @@ module compressed_decoder #(
                 is_macro_instr_o = 1;
                 instr_o = instr_i;
               end else if (instr_i[12:10] == 3'b000) begin  //jt/jalt instruction
-                is_zcmt_instr_o = 1;
+                is_zcmt_instr_o = 1'b1;
               end else begin
                 illegal_instr_o = 1'b1;
               end

diff --git a/core/ex_stage.sv b/core/ex_stage.sv
@@ -321,8 +321,8 @@ module ex_stage
       .v_i,
       .debug_mode_i,
       .fu_data_i         (one_cycle_data),
-      .pc_i,
-      .is_zcmt_i,
+      .pc_i              (pc_i),
+      .is_zcmt_i         (is_zcmt_i),
       .is_compressed_instr_i,
       .branch_valid_i    (|branch_valid_i),
       .branch_comp_res_i (alu_branch_res),

diff --git a/core/id_stage.sv b/core/id_stage.sv
@@ -128,7 +128,6 @@ module id_stage #(
   logic                                          is_last_macro_instr_o;
   logic                                          is_double_rd_macro_instr_o;
   logic               [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;
-  branchpredict_sbe_t                            branch_predict;
 
   if (CVA6Cfg.RVC) begin
     // ---------------------------------------------------------

diff --git a/core/issue_stage.sv b/core/issue_stage.sv
@@ -264,7 +264,7 @@ module issue_stage
       .fu_data_o               (fu_data_o),
       .rs1_forwarding_o        (rs1_forwarding_xlen),
       .rs2_forwarding_o        (rs2_forwarding_xlen),
-      .pc_o,
+      .pc_o                    (pc_o),
       .is_zcmt_o               (is_zcmt_o),
       .is_compressed_instr_o,
       .flu_ready_i             (flu_ready_i),

diff --git a/core/zcmt_decoder.sv b/core/zcmt_decoder.sv
@@ -35,10 +35,9 @@ module zcmt_decoder #(
   }
       state_d, state_q;
   // Temporary registers
-  logic [7:0] index;  //index of instruction
   //Physical address: jvt + (index <<2)
   logic [CVA6Cfg.XLEN+1:0] table_address;  //Virtual  address: {00,Physical address}
-  logic [20:0] jump_addr;  //jump address immidiate
+  logic [31:0] jump_addr;  //jump address immidiate
 
   always_comb begin
     state_d               = state_q;
@@ -47,21 +46,22 @@ module zcmt_decoder #(
     fetch_stall_o         = is_zcmt_instr_i ? 1'b1 : 0;
 
     //cache request port
-    req_port_o.data_wdata = 1'b0;
+    req_port_o.data_wdata = '0;
     req_port_o.data_wuser = '0;
     req_port_o.data_req   = 1'b0;
     req_port_o.data_we    = 1'b0;
-    req_port_o.data_be    = 1'b0;
+    req_port_o.data_be    = '0;
     req_port_o.data_size  = 2'b10;
-    req_port_o.data_id    = 1;
-    req_port_o.kill_req   = 0;
-    req_port_o.tag_valid  = 1;
+    req_port_o.data_id    = 1'b1;
+    req_port_o.kill_req   = 1'b0;
+    req_port_o.tag_valid  = 1'b1;
 
     unique case (state_q)
       IDLE: begin
         if (is_zcmt_instr_i) begin
           if (CVA6Cfg.XLEN == 32) begin  //It is only target for 32 bit targets in cva6 with No MMU
-            table_address = {2'b00, ({jvt_i.base, jvt_i.mode} + (instr_i[9:2] << 2))};
+            // table_address = {2'b00, ({jvt_i.base, instr_i[7:2], 2'b00})};
+            table_address = {2'b00, ({jvt_i.base, jvt_i.mode} + {24'h0, instr_i[7:2], 2'b00})};
             req_port_o.address_index = table_address[9:0];
             req_port_o.address_tag = table_address[33:10];
             state_d = TABLE_JUMP;