Altera flow support (#2649)

Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap

Makefile

@@ -40,7 +40,10 @@ torture-logs   :=
 elf_file        ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
 # board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video
 BOARD          ?= genesys2
-
+ALTERA_BOARD		 ?= DK-DEV-AGF014E3ES
+ALTERA_FAMILY	 ?= "AGILEX"
+ALTERA_PART		 ?= AGFB014R24B2E2V
+PLATFORM			 = "PLAT_XILINX"
 # root path
 mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
 root-dir := $(dir $(mkfile_path))
@@ -166,17 +169,11 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv)                            \
         $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv)                         \
         $(wildcard corev_apu/axi_mem_if/src/*.sv)                                    \
+				$(wildcard corev_apu/riscv-dbg/src/*.sv)                                   \
         corev_apu/rv_plic/rtl/rv_plic_target.sv                                      \
         corev_apu/rv_plic/rtl/rv_plic_gateway.sv                                     \
         corev_apu/rv_plic/rtl/plic_regmap.sv                                         \
         corev_apu/rv_plic/rtl/plic_top.sv                                            \
-        corev_apu/riscv-dbg/src/dmi_cdc.sv                                           \
-        corev_apu/riscv-dbg/src/dmi_jtag.sv                                          \
-        corev_apu/riscv-dbg/src/dmi_jtag_tap.sv                                      \
-        corev_apu/riscv-dbg/src/dm_csrs.sv                                           \
-        corev_apu/riscv-dbg/src/dm_mem.sv                                            \
-        corev_apu/riscv-dbg/src/dm_sba.sv                                            \
-        corev_apu/riscv-dbg/src/dm_top.sv                                            \
         corev_apu/riscv-dbg/debug_rom/debug_rom.sv                                   \
         corev_apu/register_interface/src/apb_to_reg.sv                               \
         vendor/pulp-platform/axi/src/axi_multicut.sv                                 \
@@ -236,6 +233,52 @@ uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv     \
 uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv))
 
 fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/util/hpdcache_sram_1rw.sv common/local/util/hpdcache_sram_wbyteenable_1rw.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv
+
+altera_src := $(shell find $(root-dir)/corev_apu/altera/src -type f \( -name "*.v" -o -name "*.sv" -o -name "*.svh" \) -print | sed 's|//|/|g')
+altera_src += $(src)
+altera_src += $(shell find $(root-dir)/corev_apu/fpga/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
+altera_src += $(shell find $(root-dir)core/cvfpu/src/common_cells/src/ -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" -o -name "*.vhd" -o -name "*.svh" \) -print)
+altera_axi_src := $(shell find $(root-dir)/vendor/pulp-platform/axi/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
+
+altera_src += $(root-dir)corev_apu/rv_plic/rtl/top_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/tlul_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_top.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/prim_subreg_ext.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/prim_subreg.sv \
+							$(root-dir)vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv \
+							$(root-dir)riscv-dbg/src/dm_obi_top.sv \
+							$(root-dir)core/include/instr_tracer_pkg.sv \
+							$(root-dir)core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv \
+							$(root-dir)core/cache_subsystem/amo_alu.sv
+
+altera_filter := corev_apu/tb/ariane_testharness.sv \
+								corev_apu/tb/ariane_peripherals.sv \
+								corev_apu/tb/rvfi_tracer.sv \
+								corev_apu/tb/common/uart.sv \
+								corev_apu/tb/common/SimDTM.sv \
+								corev_apu/tb/common/SimJTAG.sv \
+								corev_apu/fpga/src/apb/src/apb_test.sv \
+								corev_apu/fpga/src/ariane_xilinx.sv \
+								corev_apu/fpga/ariane_peripherals_xilinx.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_cdc.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_regs.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_demux.sv \
+								corev_apu/fpga/src/gpio/test/tb_gpio.sv \
+								vendor/pulp-platform/axi/src/axi_test.sv \
+								corev_apu/riscv-dbg/src/dm_pkg.sv \
+								corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
+								corev_apu/riscv-dbg/src/dmi_jtag.sv \
+								corev_apu/fpga/src/apb_uart/src/reg_uart_wrap.sv
+
+altera_filter := $(addprefix $(root-dir), $(altera_filter))
+xil_debug_filter = $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_obi_top.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_pkg.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag_tap.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag.sv)						
+src := $(filter-out $(xil_debug_filter), $(src))
+
 fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
 
 # look for testbenches
@@ -738,7 +781,7 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co
 fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv)
 
 src/bootrom/bootrom_$(XLEN).sv:
-	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv
+	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv
 
 fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
 	@echo "[FPGA] Generate sources"
@@ -750,6 +793,19 @@ fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
 	@echo "[FPGA] Generate Bitstream"
 	$(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
 
+altera: PLATFORM := "PLAT_AGILEX"
+
+altera: $(ariane_pkg) $(src) $(fpga_src) $(src_flist)
+	@echo "[FPGA] Generate sources"
+	@echo $(ariane_pkg) > corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter), $(src_flist))		>> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter), $(src)) 	   >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(altera_filter), $(fpga_src))		 >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter) $(uart_src_sv), $(altera_src))   >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter), $(altera_axi_src))   >> corev_apu/altera/sourcelist.txt
+	@echo "[FPGA] Generate Bitstream"
+	$(MAKE) -C corev_apu/altera ALTERA_PART=$(ALTERA_PART) ALTERA_BOARD=$(ALTERA_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
+
 .PHONY: fpga
 
 build-spike:
@@ -762,6 +818,9 @@ clean:
 	$(MAKE) -C corev_apu/fpga clean
 	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) clean
 
+clean-altera: clean
+	$(MAKE) -C corev_apu/altera clean
+
 .PHONY:
 	build sim sim-verilate clean                                              \
 	$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests))             \

core/Flist.cva6

@@ -29,6 +29,8 @@
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv
 
 +incdir+${CVA6_REPO_DIR}/core/include/
 +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/

corev_apu/altera/Makefile

@@ -0,0 +1,197 @@
+# // Copyright (c) 2024 PlanV Technologies
+# // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# // Copyright and related rights are licensed under the Solderpad Hardware
+# // License, Version 0.51 (the "License"); you may not use this file except in
+# // compliance with the License.  You may obtain a copy of the License at
+# // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+# // or agreed to in writing, software, hardware and materials distributed under
+# // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# // CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# // specific language governing permissions and limitations under the License.
+
+# // Description: Makefile for Altera project
+# // Author: Mustafa Karadayi, PlanV Technology
+###################################################################
+# Project Configuration: 
+# 
+# Specify the name of the design (project) and the Quartus II
+# Settings File (.qsf)
+###################################################################
+
+PROJECT =Example-Project##mkdigitals ask for project name
+TOP_LEVEL_ENTITY = ####mkdigitals ask for the top level entity
+ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+SOURCES_FILE = ./sourcelist.txt
+# Define the output bitstream file
+BITSTREAM := $(PROJECT).sof
+###################################################################
+# Part, Family, Boardfile DE1 or DE2
+## FAMILY COMES FROM THE CALLING MAKEFILE
+## PART COMES FROM THE CALLING MAKEFILE
+## BOARDFILE COMES FROM THE CALLING MAKEFILE ## mkdigitals ask if there is a board file
+###################################################################
+
+###################################################################
+# Setup your sources here
+SRCS = $(shell cat $(SOURCES_FILE))
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and database
+# program: program your device with the compiled design
+###################################################################
+
+all: create_project \
+	write_settings \
+	write_loc_constraints \
+	write_io_standard_constraints \
+	write_ip_files \
+	write_search_paths \
+	write_source_files \
+	write_timing_constraints \
+	generate_ips \
+	sta
+
+clean:
+	$(RM) -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.summary *.smsg *.jdi $(ASSIGNMENT_FILES)
+# Capture the Quartus version
+QUARTUS_VERSION := $(shell quartus_sh --version | grep -oP 'Version \K[0-9]+\.[0-9]+')
+CURRENT_DATETIME := $(shell date +"%H:%M:%S  %B %d, %Y")
+create_project:	
+	@echo "Creating or regenerating $(PROJECT).qpf"
+	@rm -f "$(PROJECT).qpf"
+	@touch "$(PROJECT).qpf"
+	@echo "QUARTUS_VERSION = \"$(QUARTUS_VERSION)\"" >> "$(PROJECT).qpf"
+	@echo "DATE = \"$(CURRENT_DATETIME)\"" >> "$(PROJECT).qpf"
+	@echo "PROJECT_REVISION = \"$(PROJECT)\"" >> "$(PROJECT).qpf"
+
+	@echo "Creating or regenerating $(PROJECT).qsf"
+	@rm -f "$(PROJECT).qsf"
+	@touch "$(PROJECT).qsf"
+	$(QSYS_PATH)qsys-script --script=ip/interconnect.tcl
+	$(QSYS_PATH)qsys-generate interconnect.qsys --quartus_project=ip/interconnect --synthesis
+	rm -f interconnect/*.v
+	rm -f interconnect/*.vhd
+	rm -f interconnect/synth/*.v
+
+write_settings:
+	@echo "Reading from settings.csv and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+  	echo "set_global_assignment -name $$line" >> "$(PROJECT).qsf"; \
+	done < settings.csv
+
+write_loc_constraints:
+	@echo "Reading from loc_constraints.csv and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+  	echo "set_location_assignment $$line" >> "$(PROJECT).qsf"; \
+	done < loc_constraints.csv
+
+write_io_standard_constraints:
+	@echo "Reading from io_standard_constraints.csv and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+		echo "set_instance_assignment -name  $$line" >> "$(PROJECT).qsf"; \
+	done < io_standard_constraints.csv
+
+write_ip_files:
+	@echo "Reading from ip_files.csv and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+		echo "set_global_assignment -name IP_FILE $$line" >> "$(PROJECT).qsf"; \
+	done < ip_files.csv
+
+write_search_paths:
+	@echo "Reading from search_paths.csv and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+		echo "set_global_assignment -name SEARCH_PATH $$line" >> "$(PROJECT).qsf"; \
+	done < search_paths.csv
+
+write_source_files:
+	@find ./interconnect -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE)
+	@echo $(var)
+	@echo >> $(SOURCES_FILE)
+	@echo "Reading from $(SOURCES_FILE) and writing to $(PROJECT).qsf with modifications"
+	@while IFS= read -r line; do \
+		for word in $$line; do \
+			if echo "$$word" | grep -q "\.vhd$$"; then \
+				echo "set_global_assignment -name VHDL_FILE $$word" >> "$(PROJECT).qsf"; \
+			elif echo "$$word" | grep -q "\.v$$"; then \
+				echo "set_global_assignment -name VERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
+			elif echo "$$word" | grep -q "\.sv$$"; then \
+				echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
+			elif echo "$$word" | grep -q "\.svh$$"; then \
+				echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \
+			else \
+				echo "set_global_assignment -name SOURCE_FILE $$word" >> "$(PROJECT).qsf"; \
+			fi; \
+		done; \
+	done < $(SOURCES_FILE)
+
+write_timing_constraints:
+	@echo "Generating constraints file list"
+	find ./constraints -type f -name "*.sdc" -exec realpath {} \; | sed 's|^|set_global_assignment -name SDC_FILE |' >> "$(PROJECT).qsf" 
+
+generate_ips:
+	$(QSYS_PATH)qsys-script --script=ip/test_mm_ccb_0.tcl
+	$(QSYS_PATH)qsys-script --script=ip/cva6_intel_jtag_uart_0.tcl
+	$(QSYS_PATH)qsys-script --script=ip/ed_synth_emif_fm_0.tcl
+	$(QSYS_PATH)qsys-script --script=ip/emif_cal.tcl
+	$(QSYS_PATH)qsys-script --script=ip/iddr_intel.tcl
+	$(QSYS_PATH)qsys-script --script=ip/io_pll.tcl
+	$(QSYS_PATH)qsys-script --script=ip/iobuf.tcl
+	$(QSYS_PATH)qsys-script --script=ip/oddr_intel.tcl
+	$(QSYS_PATH)qsys-script --script=ip/vJTAG.tcl
+	$(QUARTUS_PATH)quartus_ipgenerate --generate_project_ip_files $(PROJECT) 
+
+map:
+	@echo "Running Quartus Map"
+	$(QUARTUS_PATH)quartus_syn $(PROJECT)
+
+fit: map
+	@echo "Running Quartus Fit"
+	$(QUARTUS_PATH)quartus_fit $(PROJECT)
+
+asm: fit
+	@echo "Running Quartus Assembly"
+	$(QUARTUS_PATH)quartus_asm $(PROJECT)
+
+sta: asm
+	@echo "Running Quartus Timing Analysis"
+	$(QUARTUS_PATH)quartus_sta $(PROJECT) --do_report_timing
+
+clean:
+	@echo "Cleaning project files"
+	rm -f $(PROJECT).qsf $(PROJECT).qpf $(PROJECT).map.rpt $(PROJECT).fit.rpt $(PROJECT).asm.rpt $(PROJECT).sta.rpt
+	rm -f interconnect.qsys*
+	rm -f *.backup
+	rm -f *.hex
+	rm -f *.txt
+	rm -f *.ip
+	rm -f ip/board.info
+	rm -f ip/*.qpf
+	rm -f ip/*.qsf
+	rm -rf ip/dni
+	rm -rf ip/.qsys_edit
+	rm -rf ip/qdb
+	rm -rf output_files
+	rm -rf db incremental_db
+	rm -rf qdb
+	rm -rf tmp-clearbox
+	rm -rf intel
+	rm -rf dni
+	rm -rf interconnect
+	rm -rf ip/interconnect
+	rm -rf cva6_intel_jtag_uart_0
+	rm -rf ed_synth_emif_fm_0
+	rm -rf emif_cal
+	rm -rf iddr_intel
+	rm -rf oddr_intel
+	rm -rf test_mm_ccb_0
+	rm -rf vJTAG
+	rm -rf interconnect
+	rm -rf io_pll
+	rm -rf iobuf
+
+	$(QUARTUS_PATH)quartus_ipgenerate --clean $(PROJECT) 
+
+.PHONY: all write_search_paths write_source_files map fit asm sta clean

corev_apu/altera/altera.cfg

@@ -0,0 +1,47 @@
+# * Copyright 2024 Thales AVS
+# * Copyright 2024 PlanV Technologies
+# * Copyright and related rights are licensed under the Solderpad Hardware
+# * License, Version 0.51 (the “License”); you may not use this file except in
+# * compliance with the License.  You may obtain a copy of the License at
+# * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+# * or agreed to in writing, software, hardware and materials distributed under
+# * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+# * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# * specific language governing permissions and limitations under the License.
+# *
+# * Author: Nicolas Levasseur, Thales AVS
+# * Additional contributions by Angela Gonzalez, PlanV Technologies
+# * Date:   8.11.2024
+# * Description: Configuration file for openocd connection
+# *
+# */
+
+adapter driver aji_client
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME agilex7
+}
+
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0xC341A0DD 
+#0xC341A0DD
+
+# VJTAG ID : 
+# -------------------------------------------------------
+# |   31 - 27    | 26 - 19 |   18 - 8    |     7 - 0    |
+# |-----------------------------------------------------|
+# | Node Version | Node ID | Node mfg_id | Node_inst_id |
+# -------------------------------------------------------
+# Info :     node  0 idcode=00406E00 position_n=0  CVA6 core #0
+
+vjtag create $_CHIPNAME.fpga.tap.cva6.0 -chain-position $_CHIPNAME.fpga.tap -expected-id 0x00406E00
+target create $_CHIPNAME.cva6.0 riscv -chain-position $_CHIPNAME.fpga.tap.cva6.0 -coreid 0 
+
+scan_chain
+
+init
+
+halt
+echo "Ready for Remote Connections"
+

corev_apu/altera/constraints/SDC1.sdc

@@ -0,0 +1,7 @@
+set_false_path -from [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] -to [get_clocks {clocks|iopll_0_outclk0}]
+set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}]
+set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {clocks|iopll_0_refclk}]
+set_false_path -from [get_clocks {clocks|iopll_0_refclk}] -to [get_clocks {clocks|iopll_0_outclk0}]
+set_disable_timing [get_ports led[*]]
+set_false_path -hold -through [get_pins -hierarchical "*async*"]
+set_max_delay -through [get_pins -hierarchical "*async*"] 5.000

corev_apu/altera/io_standard_constraints.csv

@@ -0,0 +1,7 @@
+IO_STANDARD "1.2 V" -to cpu_resetn -entity cva6_altera
+IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to pll_ref_clk_p -entity cva6_altera
+IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_ddr4_ch0_p -entity cva6_altera
+IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera
+IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera
+IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera
+IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera