[Pmp] Verif plan TXT #2457
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[Pmp] Verif plan TXT #2457
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Specify CV-X-IF version supported: 1.0.0. Mention of B extension (with includes the Zb* extensions, already in the specification). Make FENCE.T as a "should" instead of "shall" as we do not have plans to integrate it yet.
…Factorization algorithm , improve csr_updater.yaml, add spike support (openhwgroup#2372)
This MR do some cleaning on the uvm env : * fixing typo * remove unused code * printing in the right place
* Increase timeout for compliance testlist * Switch to verilator for riscv-tests-v for faster sim * fix reports for non tandem jobs
Update hpdcache_sram black box which changed with bump of hpdcache repository
* Due to the increased count of warnings, provide tail of log instead of head on the dashboard * Add tandem yaml report file on the jobs reports * Reduce UVM Verbosity on smoke gen tests
Show the config on the smoke gen dashboard report
The third optimization for Altera FPGA is to move the register file to LUTRAM. Same as before, the reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the register file. The main changes to the existing code are: Changes in ariane_regfile_fpga.sv file: The idea is the same as before, since synchronous RAM takes one clock cycle to read, we need to store the data when it is written, in case it is read right after. For this there is an auxiliary register that stores the last written data. On the read side, we need to identify if the data to be read is available in the RAM or if it is still in the auxiliary register (read after write). To compensate for the synchronous RAM delay the address is advanced one clock cycle. In this case there is a multiplexer in the output to select the block from where data is read, here we need to keep the read address for one clock cycle to select the right block when data is available. Changes in issue_read_operands.sv file: adjust address to read from register file (when synchronous RAM is used reads take one cycle, so we advance the address). Since this address is an input, we need a new input port that brings the address in advance “issue_instr_i_prev”. Changes in issue_stage.sv file: To connect the new input port that brings the address in advance “decoded_instr_i_prev”. Changes in id_stage.sv file: To output the instruction to be issued before registering it (one clock cycle in advance). A new output port is needed for this “issue_entry_o_prev” Changes in cva6.sv file: To connect the new output of the id_stage to the issue_stage to bring the address in advance to the register file (issue_entry_id_issue_prev)
* Fix rtd yaml * add rtd badge to readme
* Add riscv-isa-sim submodule * Add cmake, bison, flex, pango, gdk-pixbuf-2.0, libgdk-pixbuf2.0-0, gdk-pixbuf-2.0, libgtk2.0-dev * Update .readthedocs.yaml
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif) from `b7f57c1` to `9601c80`. - [Release notes](https://github.com/openhwgroup/core-v-verif/releases) - [Commits](openhwgroup/core-v-verif@b7f57c1...9601c80) --- updated-dependencies: - dependency-name: verif/core-v-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
cva6/core/cache_subsystem/wt_dcache_missunit.sv Line 202 in b718824 .OutWidth ($clog2(CVA6Cfg.DCACHE_SET_ASSOC)) Better to use the width parameter which already contemplates the case of 0 to avoid issues if associativity is set to 1 cva6/core/include/build_config_pkg.sv Line 134 in b718824 cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc;
in wt_axi_adapter, axi_rd_blen and axi_wr_blen are defined like this: logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; However, if AxiNumWords=1, this gives a synthesis error. This happens if the cache line is set to 64 bits (same as AXI width). It can be fixed by changing to: logic [AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords-1:0] axi_rd_blen, axi_wr_blen;
use defined adoc variable
Extraction of the PMP outside of the MMU.
Make cv64a6_imafdch_sv39 available from cva6.py
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The PMP updated has been merged ( #2528). @ASintzoff @JeanRochCoulon does the VP_TOOL update and provided tests look ok to you ? |
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This PR modifies 50k lines: too much. Maybe a rebase issue. |
OlivierBetschi
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✔️ successful run, report available here. |
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I found. This PR is related to master_when_no_mmu, while it should be master. |
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I opened a new PR against master : #2648 I think we can close this one |
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This PR aims at resolving task #1447
Here's a first version of the Verification Plan of PMP, in txt format.
It is split in 2 files:
VPTool format is undergoing on our side.
We'd like to share already the content to get first feedbacks.