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Various fixes for CVXIF following verification. #2678

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merged 3 commits into from
Dec 20, 2024
Merged

Various fixes for CVXIF following verification. #2678

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834402a
[CVXIF] Various fixes for bugs report with CVXIF's UVM agent
AyoubJalali Dec 6, 2024
6b01db0
Update options and simulators to support CVXIF's UVM agent
Gchauvon Dec 19, 2024
b396606
Merge branch 'master' into dev/cvxif_fix_rtl2
ASintzoff Dec 20, 2024
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6 changes: 0 additions & 6 deletions .gitlab-ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -250,12 +250,6 @@ cvxif-regression:
DASHBOARD_SORT_INDEX: 5
DASHBOARD_JOB_CATEGORY: "Basic"
COLLECT_SIMU_LOGS: 1
SPIKE_TANDEM: 1
parallel:
matrix:
- DV_SIMULATORS:
- "veri-testharness,spike"
- "vcs-testharness"
script:
- bash verif/regress/cvxif_verif_regression.sh
- if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
Expand Down
16 changes: 9 additions & 7 deletions core/cvxif_compressed_if_driver.sv
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Expand Up @@ -21,13 +21,14 @@ module cvxif_compressed_if_driver #(

input logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] instruction_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_i,

output logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_o,
input logic stall_i,
output logic stall_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] stall_o,
// CVXIF Compressed interface
input logic compressed_ready_i,
input x_compressed_resp_t compressed_resp_i,
Expand All @@ -43,30 +44,31 @@ module cvxif_compressed_if_driver #(
compressed_valid_o = 1'b0;
compressed_req_o.instr = '0;
compressed_req_o.hartid = hart_id_i;
stall_o = stall_i;
stall_o[0] = stall_i;
stall_o[1] = 1'b0;
if (is_illegal_i[0]) begin
compressed_valid_o = is_illegal_i[0];
compressed_valid_o = is_illegal_i[0] && instruction_valid_i[0];
compressed_req_o.instr = instruction_i[0][15:0];
is_illegal_o[0] = ~compressed_resp_i.accept;
instruction_o[0] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[0];
is_compressed_o[0] = compressed_resp_i.accept ? 1'b0 : is_compressed_i[0];
if (~stall_i) begin
// Propagate stall from macro decoder or wait for compressed ready if compressed transaction is happening.
// Stall if both instruction are illegal
stall_o[0] = (compressed_valid_o && ~compressed_ready_i);
if (CVA6Cfg.SuperscalarEn) begin
stall_o = is_illegal_i[1];
end else begin
stall_o = (compressed_valid_o && ~compressed_ready_i);
stall_o[1] = is_illegal_i[1];
end
end
end
if (CVA6Cfg.SuperscalarEn) begin
if (~is_illegal_i[0] && is_illegal_i[1]) begin // 2nd instruction is illegal
compressed_valid_o = is_illegal_i[1];
compressed_valid_o = is_illegal_i[1] && instruction_valid_i[1];
compressed_req_o.instr = instruction_i[1][15:0];
is_illegal_o[1] = ~compressed_resp_i.accept;
instruction_o[1] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[1];
is_compressed_o[1] = compressed_resp_i.accept ? 1'b0 : is_compressed_i[1];
stall_o[1] = (compressed_valid_o && ~compressed_ready_i);
end
end
end
Expand Down
2 changes: 1 addition & 1 deletion core/cvxif_issue_register_commit_if_driver.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ module cvxif_issue_register_commit_if_driver #(

// Always do commit transaction with issue
// If instruction goes to execute then it is not speculative
assign commit_valid_o = issue_valid_o;
assign commit_valid_o = issue_valid_o && issue_ready_i;
assign commit_o.hartid = issue_req_o.hartid;
assign commit_o.id = issue_req_o.id;
assign commit_o.commit_kill = 1'b0;
Expand Down
13 changes: 8 additions & 5 deletions core/id_stage.sv
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Expand Up @@ -111,11 +111,12 @@
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cvxif;

logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i;
logic stall_instr_fetch;
logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch;
logic stall_macro_deco;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;


if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
// 1. Check if they are compressed and expand in case they are
Expand Down Expand Up @@ -160,12 +161,13 @@
.x_compressed_req_t(x_compressed_req_t),
.x_compressed_resp_t(x_compressed_resp_t)
) i_cvxif_compressed_if_driver_i (
.clk_i (clk_i),

Check warning on line 164 in core/id_stage.sv

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Raw Output:
core/id_stage.sv:164:-          .clk_i             (clk_i),
core/id_stage.sv:165:-          .rst_ni            (rst_ni),
core/id_stage.sv:166:-          .hart_id_i         (hart_id_i),
core/id_stage.sv:167:-          .is_compressed_i   (is_compressed_cvxif),
core/id_stage.sv:168:-          .is_illegal_i      (is_illegal_cvxif),
core/id_stage.sv:169:-          .instruction_i     (instruction_cvxif),
core/id_stage.sv:170:-          .instruction_valid_i (fetch_entry_valid_i),
core/id_stage.sv:171:-          .is_compressed_o   (is_compressed_cmp),
core/id_stage.sv:172:-          .is_illegal_o      (is_illegal_cmp),
core/id_stage.sv:173:-          .instruction_o     (instruction),
core/id_stage.sv:174:-          .stall_i           (stall_macro_deco),
core/id_stage.sv:175:-          .stall_o           (stall_instr_fetch),
core/id_stage.sv:176:-          .compressed_ready_i(compressed_ready_i),
core/id_stage.sv:177:-          .compressed_resp_i (compressed_resp_i),
core/id_stage.sv:178:-          .compressed_valid_o(compressed_valid_o),
core/id_stage.sv:179:-          .compressed_req_o  (compressed_req_o)
core/id_stage.sv:164:+          .clk_i              (clk_i),
core/id_stage.sv:165:+          .rst_ni             (rst_ni),
core/id_stage.sv:166:+          .hart_id_i          (hart_id_i),
core/id_stage.sv:167:+          .is_compressed_i    (is_compressed_cvxif),
core/id_stage.sv:168:+          .is_illegal_i       (is_illegal_cvxif),
core/id_stage.sv:169:+          .instruction_i      (instruction_cvxif),
core/id_stage.sv:170:+          .instruction_valid_i(fetch_entry_valid_i),
core/id_stage.sv:171:+          .is_compressed_o    (is_compressed_cmp),
core/id_stage.sv:172:+          .is_illegal_o       (is_illegal_cmp),
core/id_stage.sv:173:+          .instruction_o      (instruction),
core/id_stage.sv:174:+          .stall_i            (stall_macro_deco),
core/id_stage.sv:175:+          .stall_o            (stall_instr_fetch),
core/id_stage.sv:176:+          .compressed_ready_i (compressed_ready_i),
core/id_stage.sv:177:+          .compressed_resp_i  (compressed_resp_i),
core/id_stage.sv:178:+          .compressed_valid_o (compressed_valid_o),
core/id_stage.sv:179:+          .compressed_req_o   (compressed_req_o)
.rst_ni (rst_ni),
.hart_id_i (hart_id_i),
.is_compressed_i (is_compressed_cvxif),
.is_illegal_i (is_illegal_cvxif),
.instruction_i (instruction_cvxif),
.instruction_valid_i (fetch_entry_valid_i),
.is_compressed_o (is_compressed_cmp),
.is_illegal_o (is_illegal_cmp),
.instruction_o (instruction),
Expand All @@ -182,11 +184,12 @@
.x_compressed_req_t(x_compressed_req_t),
.x_compressed_resp_t(x_compressed_resp_t)
) i_cvxif_compressed_if_driver_i (
.clk_i (clk_i),

Check warning on line 187 in core/id_stage.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
core/id_stage.sv:187:-          .clk_i             (clk_i),
core/id_stage.sv:188:-          .rst_ni            (rst_ni),
core/id_stage.sv:189:-          .hart_id_i         (hart_id_i),
core/id_stage.sv:190:-          .is_compressed_i   (is_compressed),
core/id_stage.sv:191:-          .is_illegal_i      (is_illegal),
core/id_stage.sv:192:-          .instruction_valid_i (fetch_entry_valid_i),
core/id_stage.sv:193:-          .instruction_i     (compressed_instr),
core/id_stage.sv:194:-          .is_compressed_o   (is_compressed_cmp),
core/id_stage.sv:195:-          .is_illegal_o      (is_illegal_cmp),
core/id_stage.sv:196:-          .instruction_o     (instruction),
core/id_stage.sv:197:-          .stall_i           (1'b0),
core/id_stage.sv:198:-          .stall_o           (stall_instr_fetch),
core/id_stage.sv:199:-          .compressed_ready_i(compressed_ready_i),
core/id_stage.sv:200:-          .compressed_resp_i (compressed_resp_i),
core/id_stage.sv:201:-          .compressed_valid_o(compressed_valid_o),
core/id_stage.sv:202:-          .compressed_req_o  (compressed_req_o)
core/id_stage.sv:187:+          .clk_i              (clk_i),
core/id_stage.sv:188:+          .rst_ni             (rst_ni),
core/id_stage.sv:189:+          .hart_id_i          (hart_id_i),
core/id_stage.sv:190:+          .is_compressed_i    (is_compressed),
core/id_stage.sv:191:+          .is_illegal_i       (is_illegal),
core/id_stage.sv:192:+          .instruction_valid_i(fetch_entry_valid_i),
core/id_stage.sv:193:+          .instruction_i      (compressed_instr),
core/id_stage.sv:194:+          .is_compressed_o    (is_compressed_cmp),
core/id_stage.sv:195:+          .is_illegal_o       (is_illegal_cmp),
core/id_stage.sv:196:+          .instruction_o      (instruction),
core/id_stage.sv:197:+          .stall_i            (1'b0),
core/id_stage.sv:198:+          .stall_o            (stall_instr_fetch),
core/id_stage.sv:199:+          .compressed_ready_i (compressed_ready_i),
core/id_stage.sv:200:+          .compressed_resp_i  (compressed_resp_i),
core/id_stage.sv:201:+          .compressed_valid_o (compressed_valid_o),
core/id_stage.sv:202:+          .compressed_req_o   (compressed_req_o)
.rst_ni (rst_ni),
.hart_id_i (hart_id_i),
.is_compressed_i (is_compressed),
.is_illegal_i (is_illegal),
.instruction_valid_i (fetch_entry_valid_i),
.instruction_i (compressed_instr),
.is_compressed_o (is_compressed_cmp),
.is_illegal_o (is_illegal_cmp),
Expand Down Expand Up @@ -290,19 +293,19 @@
if (issue_n[1].valid) begin
issue_n[0] = issue_n[1];
issue_n[1].valid = 1'b0;
end else if (fetch_entry_valid_i[0]) begin
end else if (fetch_entry_valid_i[0] && !stall_instr_fetch[0]) begin
fetch_entry_ready_o[0] = 1'b1;
issue_n[0] = '{1'b1, decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]};
end
end

if (!issue_n[1].valid) begin
if (fetch_entry_ready_o[0]) begin
if (fetch_entry_valid_i[1]) begin
if (fetch_entry_valid_i[1] && !stall_instr_fetch[1]) begin
fetch_entry_ready_o[1] = 1'b1;
issue_n[1] = '{1'b1, decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]};
end
end else if (fetch_entry_valid_i[0]) begin
end else if (fetch_entry_valid_i[0] && !stall_instr_fetch[0]) begin
fetch_entry_ready_o[0] = 1'b1;
issue_n[1] = '{1'b1, decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]};
end
Expand All @@ -325,7 +328,7 @@
// or the issue stage is currently acknowledging an instruction, which means that we will have space
// for a new instruction
if ((!issue_q[0].valid || issue_instr_ack_i[0]) && fetch_entry_valid_i[0]) begin
if (stall_instr_fetch) begin
if (stall_instr_fetch[0]) begin
fetch_entry_ready_o[0] = 1'b0;
end else begin
fetch_entry_ready_o[0] = 1'b1;
Expand Down
12 changes: 6 additions & 6 deletions core/issue_read_operands.sv
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Expand Up @@ -679,7 +679,7 @@ module issue_read_operands
stall_rs3[0] = 1'b0;
end
end
stall_raw[0] = stall_rs1[0] || stall_rs2[0] || stall_rs3[0];
stall_raw[0] = x_transaction_rejected ? 1'b0 : stall_rs1[0] || stall_rs2[0] || stall_rs3[0];
end

if (CVA6Cfg.SuperscalarEn) begin
Expand Down Expand Up @@ -932,16 +932,16 @@ module issue_read_operands
end
end

if (CVA6Cfg.SuperscalarEn) begin
if (!issue_ack[0]) begin
issue_ack[1] = 1'b0;
end
end
issue_ack_o = issue_ack;
// Do not acknoledge the issued instruction if transaction is not completed.
if (issue_instr_i[0].fu == CVXIF && !(x_transaction_accepted_o || x_transaction_rejected)) begin
issue_ack_o[0] = issue_instr_i[0].ex.valid && issue_instr_valid_i[0];
end
if (CVA6Cfg.SuperscalarEn) begin
if (!issue_ack_o[0]) begin
issue_ack_o[1] = 1'b0;
end
end
end

// ----------------------
Expand Down
4 changes: 2 additions & 2 deletions verif/regress/cvxif_verif_regression.sh
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Expand Up @@ -40,10 +40,10 @@ export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBO
cd verif/sim/
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=vcs-testharness,spike $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=vcs-uvm,spike --issrun_opts="+enabled_cvxif" --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld
make -C ../.. clean
make clean_all

Expand Down
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