Merge branch 'openhwgroup:main' into suse

openhwgroup · Nov 26, 2024 · c5446ed · c5446ed
2 parents 2336461 + 75c1690
commit c5446ed
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Showing 13 changed files with 40 additions and 18 deletions.
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
@@ -0,0 +1,17 @@
+# To get started with Dependabot version updates, you'll need to specify which
+# package ecosystems to update and where the package manifests are located.
+# Please see the documentation for all configuration options:
+# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file
+
+version: 2
+updates:
+  # Update git submodules to latest version
+  - package-ecosystem: "gitsubmodule"
+    directory: "/"
+    schedule:
+      interval: "weekly"
+  # Update actions in the GitHub Actions workflow files
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "weekly"
diff --git a/.gitmodules b/.gitmodules
@@ -8,9 +8,6 @@
 [submodule "addins/coremark"]
 	path = addins/coremark
 	url = https://github.com/eembc/coremark
-[submodule "addins/FreeRTOS-Kernel"]
-	path = addins/FreeRTOS-Kernel
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
 [submodule "addins/vivado-boards"]
 	path = addins/vivado-boards
 	url = https://github.com/Digilent/vivado-boards/
@@ -29,9 +26,6 @@
 	path = addins/cvw-arch-verif
 	url = https://github.com/openhwgroup/cvw-arch-verif
 	ignore = dirty
-[submodule "addins/riscvISACOV"]
-	path = addins/riscvISACOV
-	url = https://github.com/riscv-verification/riscvISACOV.git
 [submodule "addins/berkeley-softfloat-3"]
 	path = addins/berkeley-softfloat-3
 	url = https://github.com/ucb-bar/berkeley-softfloat-3.git

diff --git a/Makefile b/Makefile
@@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory
 
 SIM = ${WALLY}/sim
 
-.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
+.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean
 
-all: riscof	testfloat combined_IF_vectors zsbl coverage # benchmarks
+all: riscof	testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks
 
 # riscof builds the riscv-arch-test and wally-riscv-arch-test suites
 riscof:
@@ -36,6 +36,10 @@ embench:
 coverage:
 	$(MAKE) -C tests/coverage
 
+cvw-arch-verif:
+	$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
+
 clean:
 	$(MAKE) clean -C sim
 	$(MAKE) clean -C ${WALLY}/tests/fp
+	$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif
diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel
diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif
diff --git a/addins/riscvISACOV b/addins/riscvISACOV
diff --git a/addins/vivado-boards b/addins/vivado-boards
diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
@@ -8,6 +8,10 @@
 // Define XLEN, used in covergroups
 `define XLEN32 1
 
+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 32'h0000
+`define CLINT_BASE 64'h02000000
+
 // Unprivileged extensions
 `include "RV32I_coverage.svh"
 `include "RV32M_coverage.svh"
@@ -39,4 +43,5 @@
 `include "RV32VM_PMP_coverage.svh"
 `include "EndianU_coverage.svh"
 `include "EndianM_coverage.svh"
-`include "EndianS_coverage.svh"
+`include "EndianS_coverage.svh"
+`include "ExceptionsM_coverage.svh"
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
@@ -8,6 +8,10 @@
 // Define XLEN, used in covergroups
 `define XLEN64 1
 
+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 64'h00000000
+`define CLINT_BASE 64'h02000000
+
 // Unprivileged extensions
 `include "RV64I_coverage.svh"
 `include "RV64M_coverage.svh"
@@ -39,6 +43,7 @@
 `include "EndianU_coverage.svh"
 `include "EndianM_coverage.svh"
 `include "EndianS_coverage.svh"
+`include "ExceptionsM_coverage.svh"
 // `include "RV64VM_PMP_coverage.svh"
 // `include "RV64CBO_VM_coverage.svh"
 // `include "RV64CBO_PMP_coverage.svh"

diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c
@@ -31,7 +31,7 @@
 
 uint8_t spi_txrx(uint8_t byte) {
   spi_sendbyte(byte);
-  waittx();
+  waitrx();
   return spi_readbyte();
 }
 

diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h
@@ -106,7 +106,7 @@ static inline void waittx() {
 }
 
 static inline void waitrx() {
-  while(read_reg(SPI_IP) & 2) {}
+  while(!(read_reg(SPI_IP) & 2)) {}
 }
 
 static inline uint8_t spi_readbyte() {

diff --git a/sim/questa/wally.do b/sim/questa/wally.do
@@ -110,9 +110,8 @@ if {[lcheck lst "--fcov"]} {
          set FCvlog "+define+INCLUDE_TRACE2COV \
                 +define+IDV_INCLUDE_TRACE2COV \
                 +define+COVER_BASE_RV32I \
-                +incdir+$env(WALLY)/addins/riscvISACOV/source \
+                +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
 		"
-
     set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
 
 }

diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv
@@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)(                 // 2^M entries of N bits
 
     assign rdata = mem[raddr];
     always_ff @(posedge PCLK)
-        if (winc & ~wfull) mem[waddr] <= wdata;
+        if (winc & wen & ~wfull) mem[waddr] <= wdata;
 
     // write and read are enabled 
     always_ff @(posedge PCLK)
+1 −1		new/board_files/zybo-z7-10/A.0/board.xml
+3 −3		new/board_files/zybo-z7-10/A.0/preset.xml
+1 −1		new/board_files/zybo-z7-20/A.0/board.xml
+3 −3		new/board_files/zybo-z7-20/A.0/preset.xml