Merge pull request #1021 from jordancarlin/gcc14

Update to GCC 14

bin/wally-tool-chain-install.sh

@@ -230,9 +230,9 @@ section_header "Installing/Updating RISC-V GNU Toolchain"
 STATUS="riscv-gnu-toolchain"
 cd "$RISCV"
 # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
-if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then
+if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
     cd riscv-gnu-toolchain
-    git reset --hard && git clean -f && git checkout b488ddb #&& git pull
+    git reset --hard && git clean -f && git checkout master && git pull
     ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
     make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
     if [ "$clean" ]; then

tests/coverage/Makefile

@@ -1,35 +1,43 @@
-CEXT		:= c
-CPPEXT		:= cpp
-AEXT		:= s
-SEXT		:= S
-SRCEXT 		:= \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
-#SRCS = $(wildcard *.S)
-#PROGS = $(patsubst %.S,%,$(SRCS))
-SRCDIR = .
-SRCEXT = S
+# Disable builtin rules because they are a shorter (but incorrect) path that Make will use by default
+MAKEFLAGS += --no-builtin-rules
+SRCDIR    := .
+SRCEXT    := S
+AEXT      := s
+OBJEXT    := o
+EXEEXT    := elf
 SOURCES		?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
-OBJEXT = elf
-OBJECTS		:= $(SOURCES:.$(SEXT)=.$(OBJEXT))
+ELFS   		:= $(SOURCES:.$(SRCEXT)=.$(EXEEXT))
+OBJDUMPS  := $(addsuffix .objdump, $(ELFS))
+MEMFILES  := $(addsuffix .memfile, $(ELFS))
 
-all: $(OBJECTS)
+all: $(OBJDUMPS) $(MEMFILES)
 
+# Create dissassembly
 %.elf.objdump: %.elf
+	riscv64-unknown-elf-objdump -S -D $< > $@
+	extractFunctionRadix.sh $@
 
-# Change many things if bit width isn't 64
-%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
-	riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../examples/link/link.ld $<
-	riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
-	riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
-	extractFunctionRadix.sh $@.objdump
-
-sim: %.elf
+# Create memfile
+%.elf.memfile: %.elf
+	riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
+
+# Link object file to create executable
+.PRECIOUS: %.$(EXEEXT)
+%.$(EXEEXT): %.$(OBJEXT)
+	riscv64-unknown-elf-gcc -g -o $@ -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o
+
+# Assemble into object files
+%.$(OBJEXT): %.$(AEXT)
+	riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $<
+
+# Preprocess assembly files
+%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h
+	riscv64-unknown-elf-gcc -E -g -o $@ $<
+
+sim: %.$(EXEEXT)
 	spike +signature=%.signature.output +signature-granularity=8 %.elf
 	diff --ignore-case %.signature.output %.reference_output || exit
 	echo "Signature matches! Success!"
 
 clean:
-	rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile
-
-
-
+	rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s

tests/coverage/WALLY-init-lib.h

@@ -7,20 +7,20 @@
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
-// 
+//
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
 // may obtain a copy of the License at
 //
 // https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -41,21 +41,21 @@
     csrw medeleg, zero  # Don't delegate exceptions
 #    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
 #    li t1, 0x02004000   # MTIMECMP in CLINT
-#    sd t0, 0(t1)      
-    li t0, 0x80         
-#    li t0, 0x00         
+#    sd t0, 0(t1)
+    li t0, 0x80
+#    li t0, 0x00
     csrw mie, t0        # Enable machine timer interrupt
-    la t0, topoftrapstack 
+    la t0, topoftrapstack
     csrw mscratch, t0   # MSCRATCH holds trap stack pointer
     csrsi mstatus, 0x8  # Turn on mstatus.MIE global interrupt enable
     # set up PMP so user and supervisor mode can access full address space
     csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
-    li t0, 0xFFFFFFFF   
+    li t0, 0xFFFFFFFF
     csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
     j main              # Call main function in user test program
 
 done:
-    li a0, 4            # argument to finish program    
+    li a0, 4            # argument to finish program
     ecall               # system call to finish program
     j self_loop         # wait forever (not taken)
 
@@ -69,11 +69,11 @@
     csrr t1, mtval      # And the trap value
     bgez t0, exception  # if msb is clear, it is an exception
 
-interrupt:              # must be a timer interrupt 
+interrupt:              # must be a timer interrupt
     li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
     li t1, 0x02004000   # MTIMECMP in CLIN
-    sd t0, 0(t1)      
-    csrw stimecmp, t0   # sets stimecmp to big number so it doesnt interrupt 
+    sd t0, 0(t1)
+    csrw stimecmp, t0   # sets stimecmp to big number so it doesnt interrupt
     li t0, 32
     csrc sip, t0        # clears stimer interrupt
     j trap_return       # clean up and return
@@ -99,7 +99,7 @@ interrupt:              # must be a timer interrupt
 
 trap_return:            # return from trap handler
     csrr t0, mepc  # get address of instruction that caused exception
-    li t1, 0x20000  
+    li t1, 0x20000
     csrs mstatus, t1    # set mprv bit to fetch instruction with permission of code that trapped
     lh t0, 0(t0)   # get instruction that caused exception
     csrc mstatus, t1    # clear mprv bit to restore normal operation
@@ -139,16 +139,16 @@ trap_return:            # return from trap handler
     slli a0, a0, 16     # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
 setmsbdone:
     ret                 # return to calller
-    
-.section .tohost 
+
+.section .tohost
 tohost:                 # write to HTIF
     .dword 0
 fromhost:
     .dword 0
 
 .EQU XLEN,64
 begin_signature:
-    .fill 6*(XLEN/32),4,0xdeadbeef    # 
+    .fill 6*(XLEN/32),4,0xdeadbeef    #
 end_signature:
 
 scratch:
@@ -159,7 +159,7 @@ tohost:                 # write to HTIF
     .space 512
 topofstack:
 # And another stack for the trap handler
-.bss   
+.bss
     .space 512
 topoftrapstack:
 

tests/coverage/amoAccessFault.S

@@ -7,20 +7,20 @@
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
-// 
+//
 // Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
 // may obtain a copy of the License at
 //
 // https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -40,7 +40,7 @@ main:
     li t2, 2
     li t3, 3
     amoadd.d t3, t2, (t1)
-        
+
     fence.I
 
 finished:

tests/coverage/csrwrites.S

@@ -7,20 +7,20 @@
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
-// 
+//
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
 // may obtain a copy of the License at
 //
 // https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -44,7 +44,7 @@ main:
     li a0, 1
     ecall               # enter supervisor mode
 
-    li a0, 0            
+    li a0, 0
     ecall               # enter user mode
 
     li a0, 1

tests/coverage/dcache1.py

@@ -4,31 +4,31 @@
 # Written: avercruysse@hmc.edu 18 April 2023
 #
 # Purpose: Test Coverage for D$
-#          (For each way, trigger a CacheDataMem write enable while chip enable is low)        
+#          (For each way, trigger a CacheDataMem write enable while chip enable is low)
 #
 # A component of the CORE-V-WALLY configurable RISC-V project.
-# 
+#
 # Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 #
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
-# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-# except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+# except in compliance with the License, or, at your option, the Apache License version 2.0. You
 # may obtain a copy of the License at
 #
 # https://solderpad.org/licenses/SHL-2.1/
 #
-# Unless required by applicable law or agreed to in writing, any work distributed under the 
-# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-# either express or implied. See the License for the specific language governing permissions 
+# Unless required by applicable law or agreed to in writing, any work distributed under the
+# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific language governing permissions
 # and limitations under the License.
 ################################################
 
 import os
 
 test_name = "dcache1.S"
 dcache_num_ways = 4
-dcache_way_size_in_bytes = 4096 
+dcache_way_size_in_bytes = 4096
 # warning i$ line size is not currently parameterized.
 
 # arbitrary start location of where I send stores to.
@@ -48,7 +48,7 @@ def wl(line="", comment=None, fname=test_name):
         to_write = " " * indent + line + comment + "\n"
         f.write(to_write)
 
-    
+
 def write_repro_instrs():
     """
     Assumes that the store location has been fetched to d$, and is in t0.
@@ -72,7 +72,7 @@ def write_repro_instrs():
     wl(comment="This file is generated by dcache1.py (run that script manually)")
     wl('#include "WALLY-init-lib.h"')
     wl('main:')
-    
+
     # excercise all 4 D$ ways. If they're not all full, it uses the first empty.
     # So we are sure all 4 ways are exercised.
     for i in range(dcache_num_ways):
@@ -82,5 +82,5 @@ def write_repro_instrs():
         wl(comment=f"i$ boundary, way test #{i+1}")
         write_repro_instrs()
         mem_addr += dcache_way_size_in_bytes  # so that we excercise a new D$ way.
-    
+
     wl("j done")

tests/coverage/dcache2.S

@@ -4,47 +4,47 @@
 // Written: avercruysse@hmc.edu 18 April 2023
 //
 // Purpose: Test Coverage for D$
-//          (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)        
+//          (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
-// 
+//
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
 // may obtain a copy of the License at
 //
 // https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 #include "WALLY-init-lib.h"
 main:
-        // way 0 
+        // way 0
         li t0, 0x80100770
         sd zero, 0(t0)
         sd zero, 1(t0)
 
-        // way 1 
+        // way 1
         li t0, 0x80101770
         sd zero, 0(t0)
         sd zero, 1(t0)
 
-        // way 2 
+        // way 2
         li t0, 0x80102770
-        sd zero, 0(t0)        
+        sd zero, 0(t0)
         sd zero, 1(t0)
 
         // way 3
         li t0, 0x80103770
         sd zero, 0(t0)
         sd zero, 1(t0)
-        
+
         j done