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    56 repositories

    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
      SystemVerilog
      •
      Other
      •178•0•0•0•Updated Oct 3, 2024Oct 3, 2024

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •19•0•0•0•Updated Oct 3, 2024Oct 3, 2024

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •679•2•0•0•Updated Oct 1, 2024Oct 1, 2024

    • riscv-iommu

      Public
      IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
      SystemVerilog
      •
      Apache License 2.0
      •14•0•0•0•Updated Sep 30, 2024Sep 30, 2024

    • riscv-ci-partners

      Public
      RISC-V CI Partners Project
      HTML
      •
      MIT License
      •0•2•0•1•Updated Sep 26, 2024Sep 26, 2024

    • Llava

      Public
      Jupyter Notebook
      •1•0•0•0•Updated Sep 24, 2024Sep 24, 2024

    • Infinite-ISP_FPGABinaries

      Public
      Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit
      fpgaxilinxxilinx-fpgaxilinx-vivado
      Python
      •
      Apache License 2.0
      •2•4•1•1•Updated Sep 23, 2024Sep 23, 2024

    • Infinite-ISP_ReferenceModel

      Public
      A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.
      computer-visionimage-processingrtlispcamera-pipelineimage-signal-processing
      Python
      •
      Apache License 2.0
      •8•11•5•3•Updated Sep 11, 2024Sep 11, 2024

    • Infinite-ISP

      Public
      A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.
      computer-visionimage-processingispimage-signal-processorcamera-pipeline
      Python
      •
      Apache License 2.0
      •26•95•13•0•Updated Sep 4, 2024Sep 4, 2024

    • Infinite-ISP_LinuxCameraStack

      Public
      Extending Linux support to enable Infinite-ISP on FPGA for the development of a libcamera-based camera application stack.
      linuxispfpga-soclibcameracamera-applicationlinux-driver-programming
      C++
      •
      Apache License 2.0
      •0•0•2•0•Updated Aug 30, 2024Aug 30, 2024

    • clang-builtin-tutorial

      Public
      1•6•0•0•Updated Aug 28, 2024Aug 28, 2024

    • Infinite-ISP_TuningTool

      Public
      Infinite-ISP Tuning Tool is a console-based ISP (image signal processor) tuning application that is specifically designed to tune various modules in the Infinite-ISP_GM.
      computer-visionimage-processingispimage-signal-processortuning-toolcamera-pipelineisp-tuning-tool
      Python
      •
      Apache License 2.0
      •3•21•2•0•Updated Aug 26, 2024Aug 26, 2024

    • Infinite-ISP_Hardware

      Public
      Apache License 2.0
      •0•0•0•0•Updated Aug 26, 2024Aug 26, 2024

    • cvw-arch-functional-verif

      Public
      SystemVerilog
      •0•0•0•0•Updated Aug 6, 2024Aug 6, 2024

    • petalinux_kria

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Aug 2, 2024Aug 2, 2024

    • Mojo-Yolo

      Public
      Mojo
      •2•1•0•0•Updated Jul 24, 2024Jul 24, 2024

    • RISCV-10xE-DV-Hackathon

      Public
      Cohort-at-10x-Cores-VeeR-EH1
      SystemVerilog
      •
      Apache License 2.0
      •220•0•2•0•Updated Jul 1, 2024Jul 1, 2024

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      •
      Other
      •412•0•0•0•Updated Jun 28, 2024Jun 28, 2024

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •218•0•0•0•Updated Jun 27, 2024Jun 27, 2024

    • programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      HTML
      •
      Other
      •96•0•0•0•Updated Jun 12, 2024Jun 12, 2024

    • Cloud-V-git-automation

      Public
      Odoo module for integration of Cloud-V GitHub app with user repositories
      Python
      •
      Apache License 2.0
      •1•0•0•0•Updated Jun 11, 2024Jun 11, 2024

    • tutorial-llvm-pass

      Public
      C++
      •0•2•0•0•Updated May 28, 2024May 28, 2024

    • cva6-pulp

      Public
      This is the fork of CVA6 intended for PULP development.
      SystemVerilog
      •
      Other
      •679•0•0•0•Updated May 13, 2024May 13, 2024

    • LLDB

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
      Other
      •12k•1•0•0•Updated Feb 1, 2024Feb 1, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
      C
      •
      Other
      •127•0•1•8•Updated Jan 26, 2024Jan 26, 2024

    • corev-llvm-project

      Public
      Other
      •18•0•0•0•Updated Jan 17, 2024Jan 17, 2024

    • 10xcelerator

      Public
      Verilog
      •3•0•9•0•Updated Dec 8, 2023Dec 8, 2023

    • riscv-arch-test

      Public
      Assembly
      •
      Apache License 2.0
      •191•0•0•0•Updated Nov 2, 2023Nov 2, 2023

    • riscv-ctg

      Public
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •52•0•0•0•Updated Nov 1, 2023Nov 1, 2023

    • riscv-ctg-alitariq

      Public
      Fork is created for Compliance PRs
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •52•0•0•0•Updated Oct 25, 2023Oct 25, 2023