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    • C
      0000Updated Dec 21, 2024Dec 21, 2024
    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      BSD 3-Clause "New" or "Revised" License
      663000Updated Dec 17, 2024Dec 17, 2024
    • Rocket Chip Generator
      Scala
      Other
      1.1k000Updated Dec 12, 2024Dec 12, 2024
    • Wiki for documenting Rocket-Chip
      CSS
      0000Updated Nov 26, 2024Nov 26, 2024
    • notes

      Public
      Notes about how to make all of the tools in Constellation-FPGA work
      TeX
      0000Updated Aug 19, 2024Aug 19, 2024
    • rocc-docs

      Public
      Wiki for documenting Rocket-Chip's RoCC Interface
      CSS
      0000Updated Jan 9, 2024Jan 9, 2024
    • GNU toolchain for RISC-V, including GCC
      C
      Other
      1.2k000Updated Jun 20, 2022Jun 20, 2022
    • RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
      C
      GNU General Public License v2.0
      234000Updated Jun 20, 2022Jun 20, 2022
    • Spike, a RISC-V ISA Simulator
      C
      Other
      876000Updated Jun 20, 2022Jun 20, 2022
    • C
      Other
      469000Updated Jun 20, 2022Jun 20, 2022
    • RISC-V Opcodes
      Python
      Other
      305000Updated Jun 20, 2022Jun 20, 2022
    • riscv-gcc

      Public
      GNU General Public License v2.0
      274000Updated Jun 17, 2022Jun 17, 2022
    • DejaGnu RISC-V port
      TeX
      GNU General Public License v3.0
      78000Updated May 23, 2022May 23, 2022
    • RISC-V port of newlib
      C
      GNU General Public License v2.0
      118000Updated Mar 15, 2022Mar 15, 2022
    • RISC-V port of GNU's libc
      85000Updated Mar 19, 2021Mar 19, 2021
    • RISC-V Tools (ISA Simulator and Tests)
      Shell
      447000Updated Aug 21, 2020Aug 21, 2020