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    • VGA driver.
      SystemVerilog
      MIT License
      1100Updated Oct 6, 2019Oct 6, 2019
    • Documentation for ZanPU.
      0400Updated Sep 20, 2019Sep 20, 2019
    • diagram

      Public
      Data path for single cycle CPU, pipelined ZanPU and pipelined ZanPU with hazard control.
      0100Updated Sep 16, 2019Sep 16, 2019
    • A classic implementation of a classic five stage RISC pipeline CPU.
      Verilog
      MIT License
      32200Updated Sep 11, 2019Sep 11, 2019
    • Vivado example repository.
      Verilog
      MIT License
      0300Updated Aug 27, 2019Aug 27, 2019